os.path.join(sSourceDir, 'BaudGen.vhd'))
oBaudGen = vhdlFile.vhdlFile(lBaudGen)
oBaudGen.set_indent_map(dIndentMap)

lBoardCpu, eBoardCpuError = vhdlFile.utils.read_vhdlfile(
    os.path.join(sSourceDir, 'Board_cpu.vhd'))
oBoardCpu = vhdlFile.vhdlFile(lBoardCpu)
oBoardCpu.set_indent_map(dIndentMap)

lDataCore, eDataCoreError = vhdlFile.utils.read_vhdlfile(
    os.path.join(sSourceDir, 'data_core.vhd'))
oDataCore = vhdlFile.vhdlFile(lDataCore)
oDataCore.set_indent_map(dIndentMap)

oConfig = utils.read_configuration(
    os.path.join(os.path.dirname(__file__), '..', '..', '..', '..', 'styles',
                 'indent_only.yaml'))

oSeverityList = severity.create_list({})


class testCodeExample(unittest.TestCase):
    def setUp(self):
        self.assertIsNone(eBaudGenError)
        self.assertIsNone(eBoardCpuError)
        self.assertIsNone(eDataCoreError)

    def test_baudgen(self):
        oRuleList = rule_list.rule_list(oBaudGen, oSeverityList)
        oRuleList.configure(oConfig)
        oRuleList.fix(7, oConfig.dConfig['skip_phase'])
oDebouncer = vhdlFile.vhdlFile(lDebouncer)
lVgatop = utils.read_vhdlfile(os.path.join(sSourceDir, 'VGA_Top.vhd'))
oVgatop = vhdlFile.vhdlFile(lVgatop)
lPointer = utils.read_vhdlfile(os.path.join(sSourceDir, 'Pointer.vhd'))
oPointer = vhdlFile.vhdlFile(lPointer)
lFreqDiv = utils.read_vhdlfile(os.path.join(sSourceDir, 'FreqDiv.vhd'))
oFreqDiv = vhdlFile.vhdlFile(lFreqDiv)
lSynchronizer = utils.read_vhdlfile(
    os.path.join(sSourceDir, 'Synchronizer.vhd'))
oSynchronizer = vhdlFile.vhdlFile(lSynchronizer)
lFrameBuffer = utils.read_vhdlfile(os.path.join(sSourceDir,
                                                'FrameBuffer2.vhd'))
oFrameBuffer = vhdlFile.vhdlFile(lFrameBuffer)

dConfig = utils.read_configuration(
    os.path.join(os.path.dirname(__file__), '..', '..', '..', '..', 'styles',
                 'jcl.yaml'))
dConfig['debug'] = False


class testCodeExample(unittest.TestCase):
    def test_bresenhamer(self):
        oRuleList = rule_list.rule_list(oBresenhamer)
        oRuleList.configure(dConfig)
        oRuleList.fix()
        lExpected = ['']
        utils.read_file(
            os.path.join(os.path.dirname(__file__), 'Bresenhamer.fixed.vhd'),
            lExpected)
        for iLineNumber, sLine in enumerate(lExpected):
            self.assertEqual(oBresenhamer.lines[iLineNumber].line, sLine)