def test_fix_012(self):
oRule = whitespace.rule_012()
self.assertTrue(oRule)
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' a <= b;')) #1
oFile.lines.append(line.blank_line()) #2
oFile.lines.append(line.blank_line()) #3
oFile.lines.append(line.blank_line()) #4
oFile.lines.append(line.blank_line()) #5
oFile.lines.append(line.line(' c <= d;')) #6
oFile.lines.append(line.line(' a <= b;')) #7
oFile.lines.append(line.blank_line()) #8
oFile.lines.append(line.line(' c <= d;')) #9
oFile.lines.append(line.blank_line()) #10
oFile.lines.append(line.blank_line()) #11
oFile.lines.append(line.line(' a <= b;')) #12
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[1].line,' a <= b;') #1
self.assertEqual(oFile.lines[2].isBlank,True) #2
self.assertEqual(oFile.lines[3].line,' c <= d;') #3
self.assertEqual(oFile.lines[4].line,' a <= b;') #4
self.assertEqual(oFile.lines[5].isBlank,True) #5
self.assertEqual(oFile.lines[6].line,' c <= d;') #6
self.assertEqual(oFile.lines[7].isBlank,True) #7
self.assertEqual(oFile.lines[8].line,' a <= b;') #8
def test_rule_020(self):
oRule = component.rule_020()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
dExpected = [{
'lines': [{
'number': 12,
'keyword_column': 31,
'before_keyword_column': 30
}, {
'number': 14,
'keyword_column': 32,
'before_keyword_column': 30
}],
'max_keyword_column':
32,
'max_before_keyword_column':
30
}]
lFileComment = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'component_comment_test_input.vhd'))
oFileComment = vhdlFile.vhdlFile(lFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_029(self):
oRule = instantiation.rule_029()
lFileComment = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'instantiation_comment_test_input.vhd'))
oFileComment = vhdlFile.vhdlFile(lFileComment)
oRule.fix(oFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, [])
self.assertEqual(
oFileComment.lines[7].line,
' generic_1 : std_logic := \'0\'; -- This should be removed')
self.assertEqual(
oFileComment.lines[12].line,
' port_2 : in std_logic;-- This should be removed')
self.assertEqual(
oFileComment.lines[14].line,
' port_4 : out std_logic; -- This should be removed')
self.assertEqual(
oFileComment.lines[24].line,
' generic_1 => \'0\', -- This should be removed')
self.assertEqual(oFileComment.lines[29].line,
' port_2 => \'1\', -- This should be removed')
self.assertEqual(oFileComment.lines[31].line,
' port_4 => \'1\' -- This should be removed')
def test_fix_rule_020(self):
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','if_statement','if_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
oRule = if_statement.rule_020()
dExpected = []
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_007_case(self):
lFileCase = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'if_case_test_input.vhd'))
oFileCase = vhdlFile.vhdlFile(lFileCase)
oRule = if_statement.rule_007()
dExpected = []
oRule.fix(oFileCase)
oRule.analyze(oFileCase)
self.assertEqual(oRule.violations, dExpected)
self.assertTrue(oFileCase.lines[18].isBlank)
def test_is_no_blank_line_after(self):
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
oFile.lines.append(line.line('Simple line'))
oFile.lines.append(line.blank_line())
oRule = no_blank_check_rule()
self.assertEqual(oRule.violations, [])
oRule.analyze(oFile)
self.assertEqual(oRule.violations, [1])
def test_fix_rule_029(self):
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','if_statement','if_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
oRule = if_statement.rule_029()
self.assertEqual(oFile.lines[14].line, ' g = 34 or x = 3000 THEN')
dExpected = []
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[14].line, ' g = 34 or x = 3000 then')
def test_rule_029(self):
oRule = instantiation.rule_029()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'instantiation')
self.assertEqual(oRule.identifier, '029')
lFileComment = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'instantiation_comment_test_input.vhd'))
oFileComment = vhdlFile.vhdlFile(lFileComment)
dExpected = ['22-32']
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_021(self):
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','if_statement','if_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
oRule = if_statement.rule_021()
dExpected = []
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[105].line, ' if (a = 2) then b <= \'1\'; ')
self.assertEqual(oFile.lines[106].line, 'else b <= \'0\'; end if;')
self.assertEqual(oFile.lines[106].indentLevel, oFile.lines[105].indentLevel)
def test_fix_rule_022(self):
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','if_statement','if_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
oRule = if_statement.rule_022()
dExpected = []
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[102].line, ' else')
self.assertEqual(oFile.lines[103].line, ' g <= x;')
self.assertEqual(oFile.lines[103].indentLevel, oFile.lines[102].indentLevel + 1)
def test_fix_rule_016(self):
lFile_rule_016 = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'port',
'port_test_input.vhd'))
oFile_rule_016 = vhdlFile.vhdlFile(lFile_rule_016)
oRule = port.rule_016()
oRule.fix(oFile_rule_016)
oRule.analyze(oFile_rule_016)
self.assertEqual(oRule.violations, [])
self.assertEqual(oFile_rule_016.lines[140].indentLevel + 1,
oFile_rule_016.lines[141].indentLevel)
def test_rule_020(self):
oRule = component.rule_020()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
dExpected = ['5-16']
lFileComment = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'component_comment_test_input.vhd'))
oFileComment = vhdlFile.vhdlFile(lFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_007(self):
oRule = whitespace.rule_007()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '007')
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' This is a test,of commas (failure )'))
oFile.lines.append(line.line(' This is a test, of commas (pass)'))
oFile.lines.append(line.line(' This is a test of commas,(failure )'))
oFile.lines.append(line.line(' This is a test of commas -- 1,2,3,4 (PASS)'))
oFile.lines.append(line.line(' ) pass'))
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_001(self):
oRule = whitespace.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '001')
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' This is a test of ending whitespace'))
oFile.lines.append(line.line(' This is a test of ending whitespace '))
oFile.lines.append(line.line(' This is a test of ending whitespace'))
oFile.lines.append(line.line(' This is a test of ending whitespace '))
oFile.lines.append(line.line(' This is a test of ending whitespace'))
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_008(self):
oRule = whitespace.rule_008()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '008')
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line('A std_logic_vector (7 downto 0)'))
oFile.lines.append(line.line(' std_logic_vector(7 downto 0)'))
oFile.lines.append(line.line(' std_logic_vector (7 downto 0)'))
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[1].line, 'A std_logic_vector(7 downto 0)')
self.assertEqual(oFile.lines[2].line, ' std_logic_vector(7 downto 0)')
self.assertEqual(oFile.lines[3].line, ' std_logic_vector(7 downto 0)')
def test_fix_010(self):
oRule = whitespace.rule_010()
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' a <= b &c -- this is an &comment'))
oFile.lines.append(line.line(' a <= b &c&d&e -- this should not be &caught '))
oFile.lines.append(line.line(' a <= b &c'))
oFile.lines.append(line.line(' a <= b &'))
oFile.lines.append(line.line(' a <= b & '))
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[1].line, ' a <= b & c -- this is an &comment')
self.assertEqual(oFile.lines[2].line, ' a <= b & c & d & e -- this should not be &caught ')
self.assertEqual(oFile.lines[3].line, ' a <= b & c')
self.assertEqual(oFile.lines[4].line, ' a <= b &')
self.assertEqual(oFile.lines[5].line, ' a <= b & ')
def test_fix_004(self):
oRule = whitespace.rule_004()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '004')
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' This is a test of commas,'))
oFile.lines.append(line.line(' This is a test of commas ,'))
oFile.lines.append(line.line(' This is a test of commas,'))
oFile.lines.append(line.line(' This is a test of commas ,'))
oFile.lines.append(line.line(' This is a test, of commas'))
oFile.lines.append(line.line(' This is a test , of commas'))
oFile.lines.append(line.line(' This is a test, of commas -- This is a comment ,'))
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[7].line, ' This is a test, of commas -- This is a comment ,')
import os
import unittest
from vsg import vhdlFile
from vsg import rule_list
from vsg.tests import utils
lBaudGen = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'BaudGen.vhd'))
oBaudGen = vhdlFile.vhdlFile(lBaudGen)
lBoardCpu = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'Board_cpu.vhd'))
oBoardCpu = vhdlFile.vhdlFile(lBoardCpu)
lDataCore = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'data_core.vhd'))
oDataCore = vhdlFile.vhdlFile(lDataCore)
class testCodeExample(unittest.TestCase):
def test_baudgen(self):
oRuleList = rule_list.rule_list(oBaudGen)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'BaudGen.fixed.vhd'),
lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oBaudGen.lines[iLineNumber].line, sLine)
def test_board_cpu(self):
oRuleList = rule_list.rule_list(oBoardCpu)
import os
import unittest
from vsg import vhdlFile
from vsg.tests import utils
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','code_tags','code_tag_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
class testCodeTags(unittest.TestCase):
def test_hasCodeTag(self):
lExpected = []
lExpected.extend(range(2, 6))
lExpected.extend(range(10, 18))
lExpected.extend(range(20, 33))
# Generic actual list
lActual = []
for iIndex, oLine in enumerate(oFile.lines):
if oLine.hasCodeTag:
lActual.append(iIndex)
# Compare
self.assertEqual(lActual, lExpected)
def test_library_008_tag(self):
lExpected = []
lExpected.extend(range(2, 6))
# Generic actual list
lActual = []
import os
import unittest
from vsg import vhdlFile
from vsg.tests import utils
lFileBlock = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','block','block_test_input.vhd'))
oFileBlock = vhdlFile.vhdlFile(lFileBlock)
class testVhdlFileMethods(unittest.TestCase):
def test_insideBlock_assignment(self):
lExpected = range(10,29)
lActual = [i for i, l in enumerate(oFileBlock.lines) if l.insideBlock]
self.assertSequenceEqual(lActual, lExpected)
def test_isBlockBegin_assignment(self):
lExpected = [18]
lActual = [i for i, l in enumerate(oFileBlock.lines) if l.isBlockBegin]
self.assertEqual(lActual, lExpected)
def test_isBlockKeyword_assignment(self):
lExpected = [10]
lActual = [i for i, l in enumerate(oFileBlock.lines) if l.isBlockKeyword]
self.assertEqual(lActual, lExpected)
def test_isEndBlock_assignment(self):
lExpected = [28]
lActual = [i for i, l in enumerate(oFileBlock.lines) if l.isEndBlock]
self.assertEqual(lActual, lExpected)
import os
import unittest
import sys
sys.path.append('vsg')
from vsg.rules import subtype
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'type_definition',
'type_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
lFilePrefix = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'subtype_prefix_test_input.vhd'))
oFilePrefix = vhdlFile.vhdlFile(lFilePrefix)
class testRuleSubtypeMethods(unittest.TestCase):
def test_rule_001(self):
oRule = subtype.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'subtype')
self.assertEqual(oRule.identifier, '001')
dExpected = [51]
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
import os
import unittest
from vsg.rules import when
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
oFile = vhdlFile.vhdlFile(
utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'when_test_input.vhd')))
class testRuleWhenMethods(unittest.TestCase):
def test_rule_001(self):
oRule = when.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'when')
self.assertEqual(oRule.identifier, '001')
dExpected = [14, 15, 16]
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
import os
import unittest
import sys
sys.path.append('vsg')
from vsg.rules import signal
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'signal_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
class testRuleSignalMethods(unittest.TestCase):
def test_rule_001(self):
oRule = signal.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '001')
lExpected = utils.add_violation_list([6, 8, 15])
oRule.analyze(oFile)
self.assertEqual(oRule.violations, lExpected)
def test_rule_002(self):
oRule = signal.rule_002()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '002')
import os
import unittest
from vsg.rules import concurrent
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'concurrent_007_test_input.vhd'))
class testRuleConcurrentMethods(unittest.TestCase):
def setUp(self):
self.oFile = vhdlFile.vhdlFile(lFile)
def test_rule_007_w_default_options(self):
oRule = concurrent.rule_007()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'concurrent')
self.assertEqual(oRule.identifier, '007')
lExpected = []
dViolation = utils.add_violation(10)
dViolation['slice_index'] = [43]
lExpected.append(dViolation)
dViolation = utils.add_violation(11)
dViolation['slice_index'] = [43]
lExpected.append(dViolation)
dViolation = utils.add_violation(16)
import os
import unittest
from vsg.rules import if_statement
from vsg import vhdlFile
from vsg import rule_list
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'if_statement',
'if_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
lFileCase = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'if_statement',
'if_case_test_input.vhd'))
oFileCase = vhdlFile.vhdlFile(lFileCase)
lFileCompress = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'if_compressed_line_test_input.vhd'))
oFileCompress = vhdlFile.vhdlFile(lFileCompress)
lFileNested = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), 'if_nested_test_input.vhd'))
oFileNested = vhdlFile.vhdlFile(lFileNested)
class testFixRuleIfMethods(unittest.TestCase):
def test_fix_rule_001(self):
oRule = if_statement.rule_001()
dExpected = []
import os
import unittest
from vsg.rules import while_loop
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(os.path.join(os.path.dirname(__file__),'..','while_loop','while_loop_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
class testRuleWhileLoopMethods(unittest.TestCase):
def test_rule_001(self):
oRule = while_loop.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'while_loop')
self.assertEqual(oRule.identifier, '001')
dExpected = [13]
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_rule_002(self):
oRule = while_loop.rule_002()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'while_loop')
self.assertEqual(oRule.identifier, '002')
dExpected = [19]
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def setUp(self):
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'consistent_case_test_input.vhd'))
self.oFile = vhdlFile.vhdlFile(lFile)
import os
import unittest
from vsg import vhdlFile
from vsg.tests import utils
lFileConcurrent = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'concurrent',
'concurrent_test_input.vhd'))
oFileConcurrent = vhdlFile.vhdlFile(lFileConcurrent)
class testVhdlFileMethods(unittest.TestCase):
def test_insideConcurrent_assignment(self):
lExpected = [
6, 7, 8, 9, 10, 11, 23, 24, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36,
38, 39, 40, 41, 42, 44, 45, 46, 48, 50, 51, 52, 53, 54, 55
]
# Generic actual list
lActual = []
for iIndex, oLine in enumerate(oFileConcurrent.lines):
if oLine.insideConcurrent:
lActual.append(iIndex)
# Compare
self.assertEqual(lActual, lExpected)
def test_isConcurrentBegin_assignment(self):
lExpected = [
6, 7, 8, 9, 11, 23, 24, 26, 32, 33, 34, 35, 38, 39, 42, 44, 45, 48,
50
]
import os
import unittest
from vsg.rules import port
from vsg import vhdlFile
from vsg.tests import utils
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'port',
'port_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
class testRulePortMethods(unittest.TestCase):
def test_rule_001(self):
oRule = port.rule_001()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'port')
self.assertEqual(oRule.identifier, '001')
dExpected = utils.add_violation_list([25, 56])
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_rule_002(self):
oRule = port.rule_002()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'port')
self.assertEqual(oRule.identifier, '002')
import os
import unittest
from vsg.rules import function
from vsg import vhdlFile
from vsg.tests import utils
# Read in test file used for all tests
lFile = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__), '..', 'function',
'function_test_input.vhd'))
oFile = vhdlFile.vhdlFile(lFile)
lFileMultiple = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'function_multiple_parameters_test_input.vhd'))
oFileMultiple = vhdlFile.vhdlFile(lFileMultiple)
class testFixRuleFunctionMethods(unittest.TestCase):
def test_fix_rule_001(self):
oRule = function.rule_001()
dExpected = []
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_002(self):
oRule = function.rule_002()
dExpected = []
oRule.fix(oFile)
