def update_lct_file_if_necessary(lct_file, goal):
if goal == "Area":
setting = "Nodes_collapsing_mode = Area;"
else:
setting = "Nodes_collapsing_mode = Fmax;"
lct_file_lines = yTools.get_original_lines(lct_file)
new_lct_lines = list()
p_start = re.compile("\[Global Constraints\]")
p_setting = re.compile("Nodes_collapsing_mode")
start = 0
for line in lct_file_lines:
line = line.strip()
if not start:
if p_start.search(line):
start = 1
new_lct_lines.append(line)
continue
elif start == 1:
if re.search("\[", line):
new_lct_lines.append(setting)
start = 2
if start == 2 or not start:
new_lct_lines.append(line)
else:
if p_setting.search(line):
continue
else:
new_lct_lines.append(line)
yTools.write_file(lct_file, new_lct_lines)
def create_lse_env_file(env_file):
lines = list()
install_dir = os.getenv("MY_CLASSIC", "NotFoundClassicInstallPath")
lines.append("FOUNDRY=%s/LSE" % install_dir)
lines.append("PATH=%s/LSE/bin/nt;%%PATH%%" % install_dir)
lines.append("")
yTools.write_file(env_file, lines)
def create_rs1_rs2_file(self):
line = "-i %(design)s.bl5 -lci %(design)s.lct -d %(sds_devfile)s -lco %(design)s.lco -html_rpt -fti "
line += "%(design)s.fti -fmt PLA -tto %(design)s.tt4 -eqn %(design)s.eq3 -tmv NoInput.tmv -rpt_num 1"
sts, line_str = yTools.get_cmd(line, self.kwargs)
if sts:
return 1
rs1_line = "%s -nojed" % line_str
rs2_line = line_str
yTools.write_file(self.kwargs.get("design") + ".rs1", rs1_line)
yTools.write_file(self.kwargs.get("design") + ".rs2", rs2_line)
def create_rsp_file(rsp_file, kwargs):
"""
puts $rspFile "-i func_sim.tt4 -lib \"$install_dir/ispcpld/dat/lc4k\"
-strategy top -sdfmdl \"$install_dir/ispcpld/dat/sdf.mdl\"
-pla func_sim.tt4 -lci func_sim.lct -prj func_sim
-dir \"$proj_dir\" -err automake.err
-log func_sim.nrp -exf register_en_set.exf
"""
# yTools.say_it(kwargs)
line = " -i %(design)s.tt4 -lib %(install_dir)s/ispcpld/dat/%(diename)s " % kwargs
line += " -strategy top -sdfmdl %(install_dir)s/ispcpld/dat/sdf.mdl " % kwargs
line += " -pla %(design)s.tt4 -lci %(design)s.lct -prj %(design)s " % kwargs
line += " -dir %(prj_dir)s -err automake.err -log %(design)s.nrp -exf %(topmodule)s.exf" % kwargs
if kwargs.get("source_format") == "Pure Verilog HDL":
line += " -netlist verilog"
yTools.write_file(rsp_file, line)
def run_scan_only(self):
_recov = yTools.ChangeDir(self.job_design)
rpt_file, lco_file = "", ""
for foo in os.listdir("."):
fext = yTools.get_fext_lower(foo)
if fext == ".rpt":
rpt_file = foo
elif fext == ".lco":
lco_file = foo
report_csv_file = os.path.abspath(
os.path.join(self.job_design, "..", "..", "report.csv"))
t = ScanClassicRpt()
t.reset()
if not os.path.isfile(report_csv_file):
yTools.write_file(report_csv_file,
",".join(["design"] + t.get_title() + ["fmax"]))
t.scan_report(rpt_file)
if os.path.isfile(lco_file):
lco_file_bak = lco_file + ".bak"
bak_ob = open(lco_file_bak, "w")
for line in open(lco_file):
if line.startswith("//"):
continue
bak_ob.write(line)
bak_ob.close()
sts, lco_dict = yTools.get_conf_options(lco_file_bak,
key_lower=False)
os.remove(lco_file_bak)
# [Timing Results]
# Fmax = 57.64;
# Logic_level = 4;
timing_results = lco_dict.get("Timing Results", dict())
fmax = timing_results.get("Fmax", "NA")
if fmax:
fmax = re.sub(";", "", fmax)
else:
fmax = "NO_LCO_FILE"
data = [os.path.basename(self.src_design)] + t.get_data() + [fmax]
yTools.append_file(report_csv_file, ",".join(data))
_recov.comeback()
def create_kwargs_for_syn(self):
t_kwargs = dict()
t_kwargs["topmodule"] = self.topmodule
t_kwargs["prj_dir"] = self.kwargs.get("prj_dir")
t_kwargs["devtargetlse"] = self.kwargs.get("devtargetlse")
t_kwargs["device"] = self.section_ds.get("device")
vhd_files = " ".join(self.kwargs.get("module"))
t_kwargs["vhd_files"] = vhd_files
t_kwargs["install_dir"] = self.kwargs.get("install_dir")
v_files = self.kwargs.get("module")
t_kwargs["v_files"] = " ".join(v_files)
h_files = self.design + ".h"
yTools.write_file(h_files, "")
t_kwargs["h_files"] = h_files
t_kwargs["lse_goal"] = self.goal
self.kwargs["env_file"] = self.topmodule + "_lse.env"
self.syn_kwargs = t_kwargs
if self.goal == "Area":
self.syn_kwargs["frequency"] = "1"
self.syn_kwargs["global"] = "Nodes_collapsing_mode = Area;"
else:
self.syn_kwargs["frequency"] = "200"
self.syn_kwargs["global"] = ""
def _run_simulation(self, sim_path, source_files, user_options):
if yTools.wrap_md(sim_path, "Simulation Path"):
return 1
if self.copy_tb_files(sim_path):
return 1
_recov = yTools.ChangeDir(sim_path)
do_lines = list()
start_source = start_tb = 0
for line in open(self.do_template):
line = line.rstrip()
if re.search("%", line):
line = line % self.sim_kwargs
do_lines.append(line)
continue
if start_source:
if self.p_src_end.search(line):
if not user_options: # RTL simulation
source_files = [
yTools.get_relative_path(item, self.job_design)
for item in source_files
]
v_v_line = self.add_vlog_vcom_lines(source_files)
do_lines += v_v_line[:]
start_source = 0
do_lines.append(line)
continue
else:
start_source = self.p_src_start.search(line)
if start_source:
do_lines.append(line)
continue
if start_tb:
if self.p_tb_end.search(line):
_kk = self.use_vhd
v_v_line = self.add_vlog_vcom_lines(self.final_tb_files)
self.use_vhd = _kk
do_lines += v_v_line[:]
start_tb = 0
do_lines.append(line)
continue
else:
start_tb = self.p_tb_start.search(line)
if start_tb:
do_lines.append(line)
continue
do_lines.append(line)
do_file = "do_%s.do" % sim_path
if self.use_vhd:
new_do_lines = [re.sub("ovi_", "", item) for item in do_lines]
else:
new_do_lines = do_lines[:]
yTools.write_file(do_file, new_do_lines)
tt = "ovi_%s" % self.kwargs.get("diename")
self.dev_lib = os.path.join(self.classic, "active-hdl", "Vlib", tt,
tt + ".LIB")
self.pri_lib = "work"
sim_cmd = "vsimsa.bat -l sim_log.txt -do %s %s %s cmd" % (
do_file, self.dev_lib, self.pri_lib)
sim_cmd = yTools.win2unix(sim_cmd, 0)
if self.use_vhd:
sim_cmd = re.sub("ovi_", "", sim_cmd)
sts = yTools.run_command(sim_cmd, "run_%s.log" % sim_path,
"run_%s.time" % sim_path)
_recov.comeback()
return sts