def _handleGetReservedAddrInfoRequest(self, request): chipsLog.debug("Reserved Address Info transaction requested") # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) responseHeader = IPbusHeader.updateWords(responseHeader, 2) # Returning zeros for the response body, as no real idea what else it should be. return TransactionElement.makeFromHeaderAndBody(responseHeader, [0,0])
def _handleReadRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) baseAddr = request.getBody()[0] chipsLog.debug("Read requested on Addr=0x" + uInt32HexStr(baseAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # The (baseAddr & 0xffffffff) forces baseAddr to be in unsigned form (i.e. 0xfffffffc, say, rather than -4) if ( baseAddr & 0xffffffff ) == 0xffffffff: # A read on this register is a Dummy Hardware Reset Request. chipsLog.info( "** Dummy Hardware reset request received! Zeroing all registers. **" ) self._registers.clear() responseBody = [] appendToResponseBody = responseBody.append # This is for a speed optimisation for offset in range(words): currentReg = baseAddr + offset # Create these registers if they don't already exist. if currentReg not in self._registers: self._registers[currentReg] = 0 appendToResponseBody(self._registers[currentReg]) return TransactionElement.makeFromHeaderAndBody( responseHeader, responseBody)
def _handleGetReservedAddrInfoRequest(self, request): chipsLog.debug("Reserved Address Info transaction requested") # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) responseHeader = IPbusHeader.updateWords(responseHeader, 2) # Returning zeros for the response body, as no real idea what else it should be. return TransactionElement.makeFromHeaderAndBody(responseHeader, [0, 0])
def _handleWriteRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) requestBody = request.getBody() baseAddr = requestBody[0] chipsLog.debug("Write requested on Addr=0x" + uInt32HexStr(baseAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(requestHeader, IPbusHeader.INFO_CODE_RESPONSE) for offset in range(words): currentReg = baseAddr + offset self._registers[currentReg] = requestBody[offset + 1] return TransactionElement.makeFromHeaderAndBody(responseHeader)
def _handleFifoWriteRequest(self, request): requestHeader = request.getHeader() requestBody = request.getBody() fifoAddr = requestBody[0] chipsLog.debug("FIFO write requested on Addr=0x" + uInt32HexStr(fifoAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # Obviously we don't really have a FIFO, we just have a single register at the address of the supposed # FIFO. So, whatever the last value written into the FIFO is, this will be the value this register will # take. We ignore all the previous "writes" to the FIFO. self._registers[fifoAddr] = requestBody[-1] return TransactionElement.makeFromHeaderAndBody(responseHeader)
def _handleWriteRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) requestBody = request.getBody() baseAddr = requestBody[0] chipsLog.debug("Write requested on Addr=0x" + uInt32HexStr(baseAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( requestHeader, IPbusHeader.INFO_CODE_RESPONSE) for offset in range(words): currentReg = baseAddr + offset self._registers[currentReg] = requestBody[offset + 1] return TransactionElement.makeFromHeaderAndBody(responseHeader)
def _handleReadModifyWriteSumRequest(self, request): requestBody = request.getBody() addr = requestBody[0] addend = requestBody[1] # The value we add to the existing value chipsLog.debug("Read/Modify/Write-sum requested on Addr=0x" + uInt32HexStr(addr)) # Create the register if it doesn't already exist. if addr not in self._registers: self._registers[addr] = 0 updatedValue = (self._registers[addr] + addend) & 0xffffffff self._registers[addr] = updatedValue # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) return TransactionElement.makeFromHeaderAndBody(responseHeader, [updatedValue])
def _handleReadModifyWriteBitsRequest(self, request): requestBody = request.getBody() addr = requestBody[0] andTerm = requestBody[1] # The and term is the bitwise complement of the register mask (i.e. mask = ~andTerm) orTerm = requestBody[2] chipsLog.debug("Read/Modify/Write-bits requested on Addr=0x" + uInt32HexStr(addr)) # Create the register if it doesn't already exist. if addr not in self._registers: self._registers[addr] = 0 updatedValue = (self._registers[addr] & andTerm) | (orTerm) self._registers[addr] = updatedValue # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) return TransactionElement.makeFromHeaderAndBody(responseHeader, [updatedValue])
def _handleFifoWriteRequest(self, request): requestHeader = request.getHeader() requestBody = request.getBody() fifoAddr = requestBody[0] chipsLog.debug("FIFO write requested on Addr=0x" + uInt32HexStr(fifoAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # Obviously we don't really have a FIFO, we just have a single register at the address of the supposed # FIFO. So, whatever the last value written into the FIFO is, this will be the value this register will # take. We ignore all the previous "writes" to the FIFO. self._registers[fifoAddr] = requestBody[-1] return TransactionElement.makeFromHeaderAndBody(responseHeader)
def _handleFifoReadRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) fifoAddr = request.getBody()[0] chipsLog.debug("FIFO read requested on Addr=0x" + uInt32HexStr(fifoAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # Create the register if they don't already exist in our memory space if fifoAddr not in self._registers: self._registers[fifoAddr] = 0 # Obviously we don't really have a FIFO, so we'll just have to return the value stored # at the FIFO's address many times... value = self._registers[fifoAddr] responseBody = [value for iReads in range(words)] return TransactionElement.makeFromHeaderAndBody(responseHeader, responseBody)
def _handleReadModifyWriteSumRequest(self, request): requestBody = request.getBody() addr = requestBody[0] addend = requestBody[1] # The value we add to the existing value chipsLog.debug("Read/Modify/Write-sum requested on Addr=0x" + uInt32HexStr(addr)) # Create the register if it doesn't already exist. if addr not in self._registers: self._registers[addr] = 0 updatedValue = (self._registers[addr] + addend) & 0xffffffff self._registers[addr] = updatedValue # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) return TransactionElement.makeFromHeaderAndBody( responseHeader, [updatedValue])
def _handleReadModifyWriteBitsRequest(self, request): requestBody = request.getBody() addr = requestBody[0] andTerm = requestBody[ 1] # The and term is the bitwise complement of the register mask (i.e. mask = ~andTerm) orTerm = requestBody[2] chipsLog.debug("Read/Modify/Write-bits requested on Addr=0x" + uInt32HexStr(addr)) # Create the register if it doesn't already exist. if addr not in self._registers: self._registers[addr] = 0 updatedValue = (self._registers[addr] & andTerm) | (orTerm) self._registers[addr] = updatedValue # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( request.getHeader(), IPbusHeader.INFO_CODE_RESPONSE) return TransactionElement.makeFromHeaderAndBody( responseHeader, [updatedValue])
def _handleFifoReadRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) fifoAddr = request.getBody()[0] chipsLog.debug("FIFO read requested on Addr=0x" + uInt32HexStr(fifoAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode( requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # Create the register if they don't already exist in our memory space if fifoAddr not in self._registers: self._registers[fifoAddr] = 0 # Obviously we don't really have a FIFO, so we'll just have to return the value stored # at the FIFO's address many times... value = self._registers[fifoAddr] responseBody = [value for iReads in range(words)] return TransactionElement.makeFromHeaderAndBody( responseHeader, responseBody)
def _handleReadRequest(self, request): requestHeader = request.getHeader() words = IPbusHeader.getWords(requestHeader) baseAddr = request.getBody()[0] chipsLog.debug("Read requested on Addr=0x" + uInt32HexStr(baseAddr)) # Response header is the request header but with the Info Code field changed to INFO_CODE_RESPONSE responseHeader = IPbusHeader.updateInfoCode(requestHeader, IPbusHeader.INFO_CODE_RESPONSE) # The (baseAddr & 0xffffffff) forces baseAddr to be in unsigned form (i.e. 0xfffffffc, say, rather than -4) if (baseAddr & 0xffffffff) == 0xffffffff: # A read on this register is a Dummy Hardware Reset Request. chipsLog.info("** Dummy Hardware reset request received! Zeroing all registers. **") self._registers.clear() responseBody = [] appendToResponseBody = responseBody.append # This is for a speed optimisation for offset in range(words): currentReg = baseAddr + offset # Create these registers if they don't already exist. if currentReg not in self._registers: self._registers[currentReg] = 0 appendToResponseBody(self._registers[currentReg]) return TransactionElement.makeFromHeaderAndBody(responseHeader, responseBody)