def get_dev():
dev = tb.get_dev()
d = {}
execfile("../terminals.py", d)
di=d["di"]
t = di["UART"].clone()
t.addr = di["UART"].addr + 2
t.name = "UART2"
di.add_child(t)
t = di["UART_CTRL"].clone()
t.addr = di["UART_CTRL"].addr + 2
t.name = "UART_CTRL2"
di.add_child(t)
dev.set_di(di)
return dev
import VUART_tb as tb
import logging, numpy
logging.basicConfig(level=logging.DEBUG)
import sim_setup
if 0:
tb.init("sim.vcd")
else:
tb.init()
dev = sim_setup.get_dev()
def test():
dev.set("UART_CTRL2", "clear_rx_buffer", 1)
x = numpy.array([ 0x6b, 0x00, 0xde, 0x07 ], dtype=numpy.uint8)
dev.write("UART", 0, x)
y = numpy.zeros(len(x), dtype=numpy.uint8)
dev.read("UART2", 0, y, 1)
if not((x == y).all()):
raise Exception("Mismatch TX="+str(x) + " RX="+str(y))
dev.set("UART_CTRL2", "clear_rx_buffer", 1)
x = 0x55
dev.set("UART", 0, x)
y = dev.get("UART2", 0, 1)
if(x != y):
raise Exception("Mismatch TX="+str(x) + " RX="+str(y))
import VUART_tb as tb
import logging, numpy
logging.basicConfig(level=logging.DEBUG)
if 1:
tb.init("sim.vcd")
else:
tb.init()
dev = tb.get_dev()
d = {}
execfile("../terminals.py", d)
dev.set_di(d["di"])
dev.set("UART_CTRL", "clk_div", 16) # speed up clock
def check():
a = (numpy.random.rand(16) * 255).astype(numpy.uint16)
dev.write("UART", 0, a)
b = numpy.zeros_like(a)
dev.read("UART", 0, b)
return (b==a).all()
def checkN(N):
for i in range(N):
if check():
passing += 1
else:
failing += 1
dev.set("UART", 0, 0x01)
