def write_read(dut):
setup_dut(dut)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
axim = AXI4_master(dut, "axi_slave_slave", dut.CLK)
dut.RST_N <= 1
yield Timer(CLK_PERIOD)
"""
setting the mem_address (0) = 5
"""
address = 0
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 1
yield axim._send_write_address(address, up.AxID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info(" address(0) was read by slave")
data = 0x0005
last_beat_of_burst = True
yield axim._send_write_data(data, up.WID, up.Baud_WSTRB,
last_beat_of_burst)
dut.log.info(" data was read by slave")
_BRESP = yield axim._get_write_response()
dut.log.info("the value of BRESP = %s" % _BRESP)
yield Timer(CLK_PERIOD * 10)
"""
reading back the data from the Baudreg
"""
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 1
yield axim._send_Read_address(address, up.AxID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info(" address(0) was read by slave")
_RDATA = yield axim._get_Read_data()
if int(str(_RDATA)[0:16], 2) == int(data):
dut.log.info("the value = %d" % int(str(_RDATA)[0:8], 2))
else:
raise TestFailure("Data read is incorrect %d " %
int(str(_RDATA)[0:8], 2))
def set_Baudreg(dut):
"""
setting the Baudrate (0x20000) = 0
"""
setup_dut(dut)
axim = AXI4_master(dut, None, dut.CLK)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
dut.RST_N <= 1
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
data = [0]
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
"""
sending the read address to AXI4 master driver to read back data
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for t in range(no_of_beats_in_burst):
dut.log.info(" data = %d" % int((str(d[t])[0:16]), 2))
def to_check_INCR_burst_works(dut):
"""
To to check INCR burst works.It should not work as uart made of FIFO
"""
setup_dut(dut)
axim = AXI4_master(dut, None, dut.CLK)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
dut.RST_N <= 1
"""
setting the Baudrate (0x20000) = 0
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
data = [0]
AxID = 2
WID = 2
burst_type = "INCR"
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for t in range(no_of_beats_in_burst):
dut.log.info(" data = %d" % int((str(d[t])[0:16]), 2))
"""
settting Rxreg(0x20004)
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20004
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
data = [61, 62, 63]
c_data = [61, 62, 63]
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
yield Timer(CLK_PERIOD * 600)
"""
reading back the data from the Txreg
"""
"""
sending the read address to AXI4 master driver to read back data
"""
address = 0x20008
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
l, h = ir.for_1_byte(address)
r_data = []
for t in range(no_of_beats_in_burst):
r_data.append(int((str(d[t])[l:h]), 2))
# dut.log.info("the value = %d" %int((str(d[t])[l:h]) , 2))
if l == 0 and h == 8:
l = 56
h = 64
else:
l = l - 8
h = h - 8
for x in range(no_of_beats_in_burst):
if r_data[x] == c_data[x]:
dut.log.info("data_%d = %d " % ((x + 1), r_data[x]))
else:
raise TestFailure(
"Data read is incorrect , therefore INCR burst will not work in case of UART slave"
)
def slave_error(dut):
"""
To check slave error
"""
setup_dut(dut)
axim = AXI4_master(dut, None, dut.CLK)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
dut.RST_N <= 1
"""
setting the Baudrate (0x20000) = 0
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
data = [0]
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for t in range(no_of_beats_in_burst):
dut.log.info(" data = %d" % int((str(d[t])[0:16]), 2))
"""
settting Rxreg(0x20004)
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20004
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
data = [61, 62, 63]
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
yield Timer(CLK_PERIOD * 600)
"""
reading back the data from the Txreg
"""
"""
sending the read address to AXI4 master driver to read back data
"""
address = 0x20008
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for t in range(no_of_beats_in_burst):
dut.log.info(" data = %d" % int((str(d[t])[0:8]), 2))
if int(str(_BRESP), 2) == 2:
raise TestFailure(
'Even though Write response = 10 (Slave Error) was dedected ,side effect was observed'
)
def max_len_burst(dut):
"""
To check the maximum length of burst
"""
setup_dut(dut)
axim = AXI4_master(dut, None, dut.CLK)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
dut.RST_N <= 1
"""
setting the Baudrate (0x20000) = 0
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
data = [0]
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type,
data, WID)
dut.log.info("the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for t in range(no_of_beats_in_burst):
dut.log.info(" data = %d" % int((str(d[t])[0:16]), 2))
for n in range(1, 18):
data = []
c_data = []
for q in range(n):
data.append(q)
"""
c_data is used to compare with the result and it is same as data
"""
c_data.append(q)
"""
settting Rxreg(0x20004)
"""
"""
sending the write address and data to the AXI4 master driver
"""
address = 0x20004
no_of_beats_in_burst = n
size_of_beat_in_bytes = 1
AxID = 2
WID = 2
_BRESP = yield axim.write_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes,
up.burst_type, data, WID)
dut.log.info(
"the value of BRESP of write transaction at address %d = %s" %
(address, _BRESP))
yield Timer(CLK_PERIOD * 200 * n)
"""
reading back the data from the Txreg
"""
"""
sending the read address to AXI4 master driver to read back data
"""
address = 0x20008
no_of_beats_in_burst = n
size_of_beat_in_bytes = 1
AxID = 3
d = yield axim.read_transaction(address, AxID, up.AxPROT,
no_of_beats_in_burst,
size_of_beat_in_bytes, up.burst_type)
dut.log.info("Burst of beat %d at address(%d) was read by slave" %
(no_of_beats_in_burst, address))
for x in range(no_of_beats_in_burst):
if int((str(d[x])[0:8]), 2) == c_data[x]:
dut.log.info("data_%d = %d " %
((x + 1), int((str(d[x])[0:8]), 2)))
else:
raise TestFailure(
"Data_%d read is incorrect.Therefore the Maximum burst lenght possible is %d "
% ((x + 1), (no_of_beats_in_burst - 1)))
def write_read(dut):
setup_dut(dut)
axim = AXI4_master(dut, None, dut.CLK)
dut.RST_N <= 0
yield Timer(CLK_PERIOD * 10)
dut.RST_N <= 1
# yield Timer(CLK_PERIOD)
"""
setting the Baudrate (0x20000) = 0
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
yield axim._send_write_address(address, up.AxID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info("Baudreg address was read by slave")
data = 0x0000
last_beat_of_burst = True
yield axim._send_write_data(data, up.WID, up.Baud_WSTRB,
last_beat_of_burst)
dut.log.info("Baudreg data was read by slave")
yield Timer(CLK_PERIOD * 50)
_BRESP = yield axim._get_write_response()
dut.log.info("the value of BRESP for Baudreg = %s" % _BRESP)
yield Timer(CLK_PERIOD * 10)
"""
reading back the data from the Baud reg
"""
address = 0x20000
no_of_beats_in_burst = 1
size_of_beat_in_bytes = 2
yield axim._send_Read_address(address, up.ARID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info("Read address was read by slave")
_RDATA = yield axim._get_Read_data()
if int(str(_RDATA)[0:16], 2) == int(data):
dut.log.info("the value of Baudreg = %d" % int(str(_RDATA)[0:16], 2))
else:
raise TestFailure("Data read form the Baudreg is incorrect %d " %
int(str(_RDATA)[0:16], 2))
yield axim._reset_handshaking_signals()
dut.WLAST <= 0
yield Timer(CLK_PERIOD * 50)
"""
1st data transfer
settting Rxreg(0x20004) = 'a'
"""
t_data = 'abc'
address = 0x20004
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
yield axim._send_write_address(address, up.AxID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info("Rxreg(0x20004) address was read by slave")
data = ord(t_data[0])
last_beat_of_burst = False
yield axim._send_write_data(data, up.WID, up.Tx_Rx_WSTRB,
last_beat_of_burst)
dut.log.info("Data of 1st data_transfer of the burst was read by slave")
yield Timer(CLK_PERIOD * 50)
# _BRESP = yield axim._get_write_response()
# dut.log.info("the value of BRESP for Data of 1st data_transfer of the burst = %s" %_BRESP)
yield axim._reset_handshaking_signals()
yield Timer(CLK_PERIOD * 200)
print("reset done")
# """
# 2nd data transfer
# settting Rxreg(0x20004) = 'b'
# """
data = ord(t_data[1])
last_beat_of_burst = False
yield axim._send_write_data(data, up.WID, up.Tx_Rx_WSTRB,
last_beat_of_burst)
dut.log.info("Data of 2nd data_transfer of the burst was read by slave")
yield Timer(CLK_PERIOD * 50)
# _BRESP = yield axim._get_write_response()
# dut.log.info("the value of BRESP for Data of 2nd data_transfer of the burst = %s" %_BRESP)
yield axim._reset_handshaking_signals()
yield Timer(CLK_PERIOD * 200)
"""
3rd data transfer
settting Rxreg(0x20004) = 'c'
"""
data = ord(t_data[2])
last_beat_of_burst = True
yield axim._send_write_data(data, up.WID, up.Tx_Rx_WSTRB,
last_beat_of_burst)
dut.log.info("Data of 3rd data_transfer of the burst was read by slave")
yield Timer(CLK_PERIOD * 50)
_BRESP = yield axim._get_write_response()
dut.log.info(
"the value of BRESP for Data of 3rd data_transfer of the burst = %s" %
_BRESP)
yield axim._reset_handshaking_signals()
yield Timer(CLK_PERIOD * 200)
"""
reading back the data from the Txreg
"""
address = 0x20008
no_of_beats_in_burst = 3
size_of_beat_in_bytes = 1
yield axim._send_Read_address(address, up.ARID, up.AxPROT,
no_of_beats_in_burst, size_of_beat_in_bytes,
up.burst_type)
dut.log.info("Txreg address was read by slave")
i = 0
while True:
_RDATA = yield axim._get_Read_data()
if chr(int((str(_RDATA)[0:8]), 2)) == t_data[i]:
dut.log.info("the value of data = %c" %
chr(int((str(_RDATA)[0:8]), 2)))
else:
raise TestFailure("Data read is incorrect %d " % int(
(str(_RDATA)[0:8]), 2))
i = i + 1
if int(dut.RLAST) == 1:
break