class BasicRom:
storage: any
output_wire: BusWire
size: int
input_wire: BusWire
def __init__(self, length: int):
self.size = length
self.storage = [None for x in range(length)]
self.output_wire = BusWire()
self.input_wire = BusWire()
def add_instruction(self, pos: int, instruction: any):
if pos > self.size or pos < 0:
return -1
self.storage[pos] = instruction
return 1
def read_instruction(self):
if self.input_wire.get_data() > self.size or self.input_wire.get_data(
) < 0:
return -1
self.output_wire.set_data(self.storage[self.input_wire.get_data()])
return 1
def notify(self):
self.read_instruction()
class BasicRam:
pages: int
rows: int
storage: any
input: BusWire
output: BusWire
opcode: BusWire
address: BusWire
def __init__(self, pages: int, rows: int):
self.storage = [[None for x in range(rows)] for y in range(pages)]
self.pages = pages
self.rows = rows
self.input = BusWire()
self.address = BusWire()
self.opcode = BusWire()
self.output = BusWire()
def store(self):
store_address = int(self.address.get_data(), 2)
page = store_address // 8
row = store_address % 8
if self.storage[page][row] is None:
self.storage[page][row] = self.input.get_data()
return (page, row)
print("RamOverload")
return (-1, -1)
def read(self):
store_address = int(self.address.get_data(), 2)
page = store_address // 8
row = store_address % 8
self.output.set_data(self.storage[page][row])
return self.storage[page][row]
def delete(self):
store_address = int(self.address.get_data(), 2)
page = store_address // 8
row = store_address % 8
self.storage[page][row] = None
def notify(self):
op = self.opcode.get_data()
if op == "10":
self.store()
if op == "11":
self.read()
class AddingUnit:
input_a: BusWire
input_b: BusWire
output: BusWire
def __init__(self):
self.input_a = BusWire()
self.input_b = BusWire()
self.output = BusWire()
def add(self):
result = int(self.input_a.get_data(), 2) + int(self.input_b.get_data(),
2)
out = bin(result)[2:].zfill(8)
self.output.set_data(out)
def notify(self):
self.add()
class ConsoleOut:
input: BusWire
input_op: BusWire
def __init__(self):
self.input = BusWire()
self.input_op = BusWire()
def out(self):
if self.input_op.get_data() == "1":
character = self.input.get_data()[:1]
data = self.input.get_data()[1:]
if character == "1":
print(chr(int(data, 2)))
if character == "0":
print(int(data, 2))
def notify(self):
self.out()
class NotGate:
input: BusWire
output: BusWire
def __init__(self):
self.input = BusWire()
self.output = BusWire()
# Bitwise and gate for n number of inputs
def calculate(self):
##inputs = list(inputs)
##output: any = self.input.get_data()
bit_len = 8
mask = int("11111111", 2)
##inputs.pop(0)
output = ~int(self.input.get_data(), 2) & mask
self.output.set_data(bin(output)[2:].zfill(8))
##self.output.set_data(output)
return bin(output)[2:].zfill(8)
def notify(self):
self.calculate()
class ControlUnit:
input_wire: BusWire
ic_out_op: BusWire
ic_out_data: BusWire
reg_demux_op_a: BusWire
reg_demux_op_b: BusWire
reg_op: BusWire
reg_mux_op_a: BusWire
reg_mux_op_b: BusWire
reg_to_adding_driver_out_op: BusWire
reg_to_adding_ram_demux_out_o: BusWire
cout_out_op: BusWire
addi_out_data: BusWire
ram_out_adress: BusWire
ram_out_op: BusWire
ldi_out_data: BusWire
adding_ldi_ram_driver_out_op_a: BusWire
adding_ldi_ram_driver_out_op_b: BusWire
adding_ldi_ram_driver_out_op_c: BusWire
four_wire_multiplexer: FourWireMultiplexer
four_wire_demultiplexer: FourWireDemultiplexer
console_out: ConsoleOut
single_wire_driver: SingleWireDriver
three_wire_driver: ThreeWireDriver
two_wire_demultiplexer: TwoWireDemultiplexer
ram: BasicRam
adding_unit: AddingUnit
register: Register
opcode: str
reg_one: str
reg_two: str
data: any
clock: Clock
def __init__(self):
self.input_wire = BusWire()
self.ic_out_op = BusWire()
self.ic_out_data = BusWire()
self.reg_demux_op_a = BusWire()
self.reg_demux_op_b = BusWire()
self.reg_op = BusWire()
self.reg_mux_op_a = BusWire()
self.reg_mux_op_b = BusWire()
self.reg_to_adding_driver_out_op = BusWire()
self.reg_to_adding_ram_demux_out_o = BusWire()
self.cout_out_op = BusWire()
self.addi_out_data = BusWire()
self.ram_out_adress = BusWire()
self.ram_out_op = BusWire()
self.ldi_out_data = BusWire()
self.adding_ldi_ram_driver_out_op_a = BusWire()
self.adding_ldi_ram_driver_out_op_b = BusWire()
self.adding_ldi_ram_driver_out_op_c = BusWire()
self.four_wire_multiplexer = None
self.four_wire_demultiplexer = None
self.register = None
self.two_wire_demultiplexer = None
self.ram = None
self.adding_unit = None
self.single_wire_driver = None
self.three_wire_driver = None
self.console_out = None
self.clock = None
self.opcode = ""
self.reg_one = ""
self.reg_two = ""
self.data = ""
def set_outputs(self):
self.resetOuts()
self.data = self.input_wire.get_data()
#print("this is data")
#print(self.input_wire.get_data())
if self.data is not None:
self.opcode = self.data[:3]
self.reg_one = self.data[3:][:2]
self.reg_two = self.data[5:][:2]
charakter_bit = self.data[7:][:1]
self.data = self.data[8:][:8]
self.choose_instruction()
def notify(self):
self.set_outputs()
def resetOuts(self):
self.ic_out_op.set_data("00000000")
self.ic_out_data.set_data("00000000")
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("00000000")
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("00000000")
self.reg_to_adding_driver_out_op.set_data("00000000")
self.reg_to_adding_ram_demux_out_o.set_data("00000000")
self.cout_out_op.set_data("00000000")
self.addi_out_data.set_data("00000000")
self.ram_out_adress.set_data("00000000")
self.ram_out_op.set_data("00000000")
self.ldi_out_data.set_data("00000000")
self.adding_ldi_ram_driver_out_op_a.set_data("00000000")
self.adding_ldi_ram_driver_out_op_b.set_data("00000000")
self.adding_ldi_ram_driver_out_op_c.set_data("00000000")
def choose_instruction(self):
if self.opcode == "001":
self.load_from_ram()
if self.opcode == "010":
self.load_immidiate()
if self.opcode == "011":
self.add_immidiate()
if self.opcode == "100":
self.store()
if self.opcode == "101":
self.console_print()
if self.opcode == "000":
self.register_copy()
if self.opcode == "111":
self.exit_programm()
def load_immidiate(self):
self.resetOuts()
self.ldi_out_data.set_data(self.data)
self.adding_ldi_ram_driver_out_op_a.set_data("11111111")
self.adding_ldi_ram_driver_out_op_b.set_data("00000000")
self.adding_ldi_ram_driver_out_op_c.set_data("00000000")
choosen_reg = int(self.reg_one, 2)
if choosen_reg == 0:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("001")
if choosen_reg == 1:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("010")
if choosen_reg == 2:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("011")
if choosen_reg == 3:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("100")
self.three_wire_driver.notify()
self.four_wire_demultiplexer.notify()
self.register.notify()
def add_immidiate(self):
self.resetOuts()
self.adding_ldi_ram_driver_out_op_a.set_data("00000000")
self.adding_ldi_ram_driver_out_op_b.set_data("11111111")
self.adding_ldi_ram_driver_out_op_c.set_data("00000000")
self.addi_out_data.set_data(self.data)
self.reg_to_adding_driver_out_op.set_data("11111111")
choosen_reg = int(self.reg_one, 2)
if choosen_reg == 0:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("11111111")
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("00000000")
self.reg_op.set_data("001")
if choosen_reg == 1:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("11111111")
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("11111111")
self.reg_op.set_data("010")
if choosen_reg == 2:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("00000000")
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("00000000")
self.reg_op.set_data("011")
if choosen_reg == 3:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("00000000")
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("11111111")
self.reg_op.set_data("100")
self.reg_to_adding_ram_demux_out_o.set_data("11111111")
self.four_wire_multiplexer.notify()
self.single_wire_driver.notify()
self.two_wire_demultiplexer.notify()
self.adding_unit.notify()
self.three_wire_driver.notify()
self.four_wire_demultiplexer.notify()
self.register.notify()
def store(self):
self.resetOuts()
self.reg_to_adding_driver_out_op.set_data("11111111")
self.reg_to_adding_ram_demux_out_o.set_data("00000000")
choosen_reg = int(self.reg_one, 2)
if choosen_reg == 0:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg == 1:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("11111111")
if choosen_reg == 2:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg == 3:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("11111111")
self.ram_out_adress.set_data(self.data)
self.ram_out_op.set_data("10")
self.four_wire_multiplexer.notify()
self.single_wire_driver.notify()
self.two_wire_demultiplexer.notify()
self.ram.notify()
def console_print(self):
self.resetOuts()
self.reg_to_adding_driver_out_op.set_data("11111111")
self.reg_to_adding_ram_demux_out_o.set_data("00000000")
choosen_reg = int(self.reg_one, 2)
if choosen_reg == 0:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg == 1:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("11111111")
if choosen_reg == 2:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg == 3:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("11111111")
self.cout_out_op.set_data("1")
self.four_wire_multiplexer.notify()
self.single_wire_driver.notify()
self.two_wire_demultiplexer.notify()
self.console_out.notify()
def load_from_ram(self):
self.resetOuts()
self.ldi_out_data.set_data(self.data)
self.adding_ldi_ram_driver_out_op_a.set_data("00000000")
self.adding_ldi_ram_driver_out_op_b.set_data("00000000")
self.adding_ldi_ram_driver_out_op_c.set_data("11111111")
choosen_reg = int(self.reg_one, 2)
if choosen_reg == 0:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("001")
if choosen_reg == 1:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("010")
if choosen_reg == 2:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("011")
if choosen_reg == 3:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("100")
self.ram_out_adress.set_data(self.data)
self.ram_out_op.set_data("11")
self.ram.notify()
self.three_wire_driver.notify()
self.four_wire_demultiplexer.notify()
self.register.notify()
def register_copy(self):
self.resetOuts()
self.adding_ldi_ram_driver_out_op_a.set_data("00000000")
self.adding_ldi_ram_driver_out_op_b.set_data("11111111")
self.adding_ldi_ram_driver_out_op_c.set_data("00000000")
self.addi_out_data.set_data("00000000")
self.reg_to_adding_driver_out_op.set_data("11111111")
choosen_reg_dest = int(self.reg_one, 2)
choosen_reg_src = int(self.reg_two, 2)
if choosen_reg_src == 0:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg_src == 1:
self.reg_mux_op_a.set_data("00000000")
self.reg_mux_op_b.set_data("11111111")
if choosen_reg_src == 2:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("00000000")
if choosen_reg_src == 3:
self.reg_mux_op_a.set_data("11111111")
self.reg_mux_op_b.set_data("11111111")
if choosen_reg_dest == 0:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("001")
if choosen_reg_dest == 1:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("11111111")
self.reg_op.set_data("010")
if choosen_reg_dest == 2:
self.reg_demux_op_a.set_data("11111111")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("011")
if choosen_reg_dest == 3:
self.reg_demux_op_a.set_data("00000000")
self.reg_demux_op_b.set_data("00000000")
self.reg_op.set_data("100")
self.reg_to_adding_ram_demux_out_o.set_data("11111111")
self.four_wire_multiplexer.notify()
self.single_wire_driver.notify()
self.two_wire_demultiplexer.notify()
self.adding_unit.notify()
self.three_wire_driver.notify()
self.four_wire_demultiplexer.notify()
self.register.notify()
def exit_programm(self):
self.clock.stop_programm()