def _BblRegAllocOrSpill(bbl: ir.Bbl, fun: ir.Fun) -> int:
"""Allocates regs to the intra bbl live ranges
Note, this runs after global register allocation has occurred
"""
# print ("\n".join(serialize.BblRenderToAsm(bbl)))
live_ranges = liveness.BblGetLiveRanges(bbl, fun, bbl.live_out)
live_ranges.sort()
for lr in live_ranges:
assert liveness.LiveRangeFlag.IGNORE not in lr.flags
# since we are operating on a BBL we cannot change LiveRanges
# extending beyond the BBL.
# reg_kinds_fixed (e.g. Machine) regs are assumed to be
# pre-allocated and will not change
if lr.reg.HasCpuReg():
lr.flags |= liveness.LiveRangeFlag.PRE_ALLOC
lr.cpu_reg = lr.reg.cpu_reg
# print (repr(lr))
if False:
print("@@@@@@@@@@@@@@@@@@@")
for lr in live_ranges:
ins = ""
if lr.def_pos >= 0 and not lr.is_use_lr():
ins = "\t# " + serialize.InsRenderToAsm(bbl.inss[lr.def_pos])
print(str(lr) + ins)
_RunLinearScan(bbl, fun, live_ranges, True,
GPR_REGS_MASK & GPR_LAC_REGS_MASK,
GPR_REGS_MASK & ~GPR_LAC_REGS_MASK,
FLT_REGS_MASK & FLT_LAC_REGS_MASK,
FLT_REGS_MASK & ~FLT_LAC_REGS_MASK)
spilled_regs = _AssignAllocatedRegsAndReturnSpilledRegs(live_ranges)
if spilled_regs:
# print (f"@@ adjusted spill count: {len(spilled_regs)} {spilled_regs}")
reg_alloc.BblSpillRegs(bbl, fun, spilled_regs, o.DK.U32, "$spill")
live_ranges = liveness.BblGetLiveRanges(bbl, fun, bbl.live_out)
live_ranges.sort()
for lr in live_ranges:
# since we are operating on a BBL we cannot change LiveRanges
# extending beyond the BBL.
# reg_kinds_fixed (e.g. Machine) regs are assumed to be
# pre-allocated and will not change
if lr.reg.HasCpuReg():
lr.flags |= liveness.LiveRangeFlag.PRE_ALLOC
lr.cpu_reg = lr.reg.cpu_reg
_RunLinearScan(bbl, fun, live_ranges, False,
GPR_REGS_MASK & GPR_LAC_REGS_MASK,
GPR_REGS_MASK & ~GPR_LAC_REGS_MASK,
FLT_REGS_MASK & FLT_LAC_REGS_MASK,
FLT_REGS_MASK & ~FLT_LAC_REGS_MASK)
spilled_regs = _AssignAllocatedRegsAndReturnSpilledRegs(live_ranges)
assert not spilled_regs
return 0
def HandleIns(ins: ir.Ins, ctx: regs.EmitContext):
print("INS: " + serialize.InsRenderToAsm(ins).strip() +
f" [{' '.join(OpTypeStr(o) for o in ins.operands)}]")
if ins.opcode in isel_tab.OPCODES_REQUIRING_SPECIAL_HANDLING:
print(f" SPECIAL")
return
pattern = isel_tab.FindMatchingPattern(ins)
print(f"PAT: reg:[{' '.join(a.name for a in pattern.type_constraints)}] "
f"op:[{' '.join(a.name for a in pattern.op_curbs)}]")
for tmpl in pattern.emit:
x64ins = tmpl.MakeInsFromTmpl(ins, ctx)
name, ops = symbolic.InsSymbolize(x64ins, True)
print(f" {name} {' '.join(ops)}")
def HandleIns(ins: ir.Ins, ctx: regs.EmitContext):
print("INS: " + serialize.InsRenderToAsm(ins).strip() +
f" [{' '.join(OpTypeStr(o) for o in ins.operands)}]")
if ins.opcode in isel_tab.OPCODES_REQUIRING_SPECIAL_HANDLING:
print(f" SPECIAL")
return
mismatches = isel_tab.FindtImmediateMismatchesInBestMatchPattern(ins)
if mismatches == isel_tab.MATCH_IMPOSSIBLE:
print(f" MATCH_IMPOSSIBLE")
elif mismatches != 0:
pattern = isel_tab.FindMatchingPattern(ins)
assert pattern is None
print(f" mismatches: {mismatches:x}")
else:
pattern = isel_tab.FindMatchingPattern(ins)
print(
f"PAT: reg:[{' '.join(a.name for a in pattern.type_constraints)}] "
f"imm:[{' '.join(a.name for a in pattern.imm_constraints)}]")
for tmpl in pattern.emit:
armins = tmpl.MakeInsFromTmpl(ins, ctx)
print(f" {disassembler.RenderInstructionSystematic(armins)}")