def sdram_test_tb():
clk, sdram_clk, sdram_return_clk, i_uart_rx, o_uart_tx = [
Signal(bool(0)) for _ in range(5)
]
@always_comb
def sdram_clk_loopback():
sdram_return_clk.next = sdram_clk
#drvrs = [TristateSignal(bool(0)) for _ in range(8)]
led_status = Signal(intbv(0, 0, 16))
pb = Signal(bool(1))
sd_intf_inst = sd_intf()
sdram_inst = sdram(sdram_clk, sd_intf_inst, show_command=False)
dut = sdram_test(clk, sdram_clk, sdram_return_clk, led_status, i_uart_rx,
o_uart_tx, pb, sd_intf_inst)
@instance
def clk_gen():
yield delay(140)
for _ in range(10000):
clk.next = not clk
yield delay(1)
pb.next = 0
for _ in range(100):
clk.next = not clk
yield delay(1)
pb.next = 1
for _ in range(6000):
clk.next = not clk
yield delay(1)
raise StopSimulation
return instances()
def sdram_test_tb():
clk, sdram_clk, sdram_return_clk = [Signal(bool(0)) for _ in range(3)]
@always_comb
def sdram_clk_loopback():
sdram_return_clk.next = sdram_clk
drvrs = [TristateSignal(bool(0)) for _ in range(8)]
led_status = Signal(intbv(0, 0, 16))
pb = Signal(bool(1))
sd_intf_inst = sd_intf()
sdram_inst = sdram(sdram_clk, sd_intf_inst, show_command=False)
dut = sdram_test(clk, sdram_clk, sdram_return_clk, drvrs[0].driver(),
drvrs[1].driver(), drvrs[2].driver(), drvrs[3].driver(),
drvrs[4].driver(), drvrs[5].driver(), drvrs[6].driver(),
drvrs[7].driver(), led_status, pb, sd_intf_inst)
@instance
def clk_gen():
yield delay(140)
for _ in range(6000):
clk.next = not clk
yield delay(1)
pb.next = 0
for _ in range(100):
clk.next = not clk
yield delay(1)
pb.next = 1
for _ in range(6000):
clk.next = not clk
yield delay(1)
raise StopSimulation
return instances()
def sdram_test_tb():
clk, sdram_clk, sdram_return_clk = [Signal(bool(0)) for _ in range(3)]
@always_comb
def sdram_clk_loopback():
sdram_return_clk.next = sdram_clk
drvrs = [TristateSignal(bool(0)) for _ in range(8)]
led_status = Signal(intbv(0,0,16))
pb = Signal(bool(1))
sd_intf_inst = sd_intf()
sdram_inst = sdram(sdram_clk, sd_intf_inst, show_command=False)
dut = sdram_test(clk, sdram_clk, sdram_return_clk, drvrs[0].driver(),
drvrs[1].driver(), drvrs[2].driver(), drvrs[3].driver(),
drvrs[4].driver(), drvrs[5].driver(), drvrs[6].driver(),
drvrs[7].driver(), led_status, pb, sd_intf_inst)
@instance
def clk_gen():
yield delay(140)
for _ in range(6000):
clk.next = not clk
yield delay(1)
pb.next = 0
for _ in range(100):
clk.next = not clk
yield delay(1)
pb.next = 1
for _ in range(6000):
clk.next = not clk
yield delay(1)
raise StopSimulation
return instances()
def sdramdev_tb():
clk, sdram_clk, sdram_return_clk = [Signal(bool(0)) for _ in range(3)]
i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall = [
Signal(bool(0)) for _ in range(5)
]
i_wb_data = Signal(intbv(0)[16:])
o_wb_data = Signal(intbv(0)[16:])
i_wb_addr = Signal(intbv(0)[32:])
i_wb_sel = Signal(intbv(0)[4:])
@always_comb
def sdram_clk_loopback():
sdram_return_clk.next = sdram_clk
#drvrs = [TristateSignal(bool(0)) for _ in range(8)]
#led_status = Signal(intbv(0,0,16))
pb = Signal(bool(1))
host_intf_inst = host_intf()
sd_intf_inst = sd_intf()
sdram_inst = sdram(sdram_clk, sd_intf_inst, show_command=False)
dut = sdramdev(clk, sdram_clk, sdram_return_clk, \
pb, sd_intf_inst,host_intf_inst,i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, \
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data, i_wb_sel)
@instance
def clk_gen():
yield delay(140)
for _ in range(2342):
clk.next = not clk
yield delay(1)
i_wb_addr.next = 3000
i_wb_data.next = 1500
i_wb_cyc.next = 1
i_wb_sel.next = 15
i_wb_stb.next = 1
i_wb_we.next = 1
for _ in range(2):
clk.next = not clk
yield delay(1)
i_wb_stb.next = 0
for _ in range(14):
clk.next = not clk
yield delay(1)
i_wb_we.next = 0
i_wb_cyc.next = 0
i_wb_sel.next = 0
"""
for _ in range(100):
clk.next = not clk
yield delay(1)
i_wb_cyc.next = 1
i_wb_sel.next = 15
i_wb_addr.next = 16777215
i_wb_data.next = 65535
for _ in range(20):
clk.next = not clk
yield delay(1)
i_wb_stb.next = 1
i_wb_we.next = 1
for _ in range(16):
clk.next = not clk
yield delay(1)
i_wb_stb.next = 0
i_wb_we.next = 0
i_wb_cyc.next = 0
i_wb_sel.next = 0
"""
for _ in range(100):
clk.next = not clk
yield delay(1)
i_wb_cyc.next = 1
i_wb_sel.next = 15
i_wb_addr.next = 3000
for _ in range(20):
clk.next = not clk
yield delay(1)
i_wb_stb.next = 1
"""
i_wb_stb needs to remain hi
longer for reads to turn off
the rd_enable
"""
for _ in range(26):
clk.next = not clk
yield delay(1)
i_wb_stb.next = 0
i_wb_cyc.next = 0
i_wb_sel.next = 0
for _ in range(1000):
clk.next = not clk
yield delay(1)
raise StopSimulation
return instances()
not both or the following error will occur
Signal has multiple drivers: host_intf_rst_i
"""
#sdramdev_inst.convert(name = 'sdcnt')
return instances()
if __name__ == '__main__':
clk, sdram_clk, sdram_return_clk = [Signal(bool(0)) for _ in range(3)]
pb = Signal(bool(1))
clk50MHz = Signal(bool(0))
clk100MHz = Signal(bool(0))
sd_intf_inst = sd_intf()
top_inst = top(clk100MHz, sdram_clk, sdram_return_clk, sd_intf_inst)
top_inst.convert(hdl="Verilog", initial_values=False, name='topcat')
"""
The following three lines if uncommented with run the simulation and
create the vcd file
"""
"""
tb = sdramdev_tb()
tb.config_sim(trace=True)
tb.run_sim()
"""
yield delay(140)
for _ in range(6000):
clk.next = not clk
yield delay(1)
pb.next = 0
for _ in range(100):
clk.next = not clk
yield delay(1)
pb.next = 1
for _ in range(6000):
clk.next = not clk
yield delay(1)
raise StopSimulation
return instances()
if __name__ == '__main__':
# Simulation(traceSignals(sdram_test_tb)).run()
clk, sdram_clk, sdram_return_clk = [Signal(bool(0)) for _ in range(3)]
d0, d1, d2, d3, d4, d5, d6, d7 = [TristateSignal(bool(0))
for _ in range(8)]
led_status = Signal(intbv(0,0,16))
pb = Signal(bool(1))
sd_intf_inst = sd_intf()
toVerilog(sdram_test, clk, sdram_clk, sdram_return_clk, d0.driver(),
d1.driver(), d2.driver(), d3.driver(),
d4.driver(), d5.driver(), d6.driver(),
d7.driver(), led_status, pb, sd_intf_inst)
