def lookup_function(view, funcname):
fi = None
filelist = view.window().lookup_symbol_in_index(funcname)
# print('Files for {0} = {1}'.format(funcname,filelist))
if filelist:
# Check if function is defined in current file first
fname = view.file_name()
flist_norm = [sublimeutil.normalize_fname(f[0]) for f in filelist]
if fname in flist_norm:
_, _, rowcol = filelist[flist_norm.index(fname)]
with open(fname, 'r') as f:
flines = str(f.read())
flines = verilogutil.clean_comment(flines)
fi = verilogutil.parse_function(flines, funcname)
if fi:
fi['fname'] = (fname, rowcol[0], rowcol[1])
# Consider first file with a valid function definition to be the correct one
else:
for f in filelist:
fname, display_fname, rowcol = f
fname_ = sublimeutil.normalize_fname(fname)
with open(fname_, 'r') as f:
flines = str(f.read())
flines = verilogutil.clean_comment(flines)
fi = verilogutil.parse_function(flines, funcname)
if fi:
# rowcols = [x for fn,_,x in filelist if fn==fname_]
fi['fname'] = (fname_, rowcol[0], rowcol[1])
break
return fi
def lookup_package(view, pkgname):
pi = None
mi = None
filelist = view.window().lookup_symbol_in_index(pkgname)
if filelist:
# Check if module is defined in current file first
fname = view.file_name()
flist_norm = [sublimeutil.normalize_fname(f[0]) for f in filelist]
if fname in flist_norm:
_, _, rowcol = filelist[flist_norm.index(fname)]
mi = verilogutil.parse_package_file(fname, pkgname)
# Consider first file with a valid module definition to be the correct one
if mi:
pi = {
'type': 'package',
'member': mi,
'fname': (fname, rowcol[0], rowcol[1])
}
else:
for f in filelist:
fname, display_fname, rowcol = f
fname = sublimeutil.normalize_fname(fname)
mi = verilogutil.parse_package_file(fname, pkgname)
if mi:
pi = {
'type': 'package',
'member': mi,
'fname': (fname, rowcol[0], rowcol[1])
}
break
# print('[SV:lookup_package] {0}'.format(pi))
return pi
def lookup_type(view, t):
ti = None
if '::' in t:
t = t.split('::')[-1]
filelist = view.window().lookup_symbol_in_index(t)
if filelist:
# Check if symbol is defined in current file first
fname = view.file_name()
flist_norm = [sublimeutil.normalize_fname(f[0]) for f in filelist]
if fname in flist_norm:
_,_,rowcol = filelist[flist_norm.index(fname)]
# print(t + ' defined in current file' + str(fname))
ti = type_info_file(view,fname,t)
if ti and ti['type'] and ti['tag']!='typedef' :
ti['fname'] = (fname,rowcol[0],rowcol[1])
# Consider first file with a valid type definition to be the correct one
else:
settings = view.settings()
file_ext = tuple(settings.get('sv.v_ext','v') + settings.get('sv.sv_ext','sv') + settings.get('sv.vh_ext','vh') + settings.get('sv.svh_ext','svh'))
for f in filelist:
fname, display_fname, rowcol = f
fname = sublimeutil.normalize_fname(fname)
if fname.lower().endswith(file_ext):
ti = type_info_file(view,fname,t)
if ti['type'] and ti['tag']!='typedef' :
ti['fname'] = (fname,rowcol[0],rowcol[1])
break
# print('[SV:lookup_type] {0}'.format(ti))
return ti
def run(self,edit):
if len(self.view.sel())==0 : return;
r = self.view.sel()[0]
scope = self.view.scope_name(r.a)
if 'meta.module.inst' not in scope:
return
# Select whole module instantiation
r = sublimeutil.expand_to_scope(self.view,'meta.module.inst',r)
txt = verilogutil.clean_comment(self.view.substr(r))
#Extract existing binding
bl = re.findall(r'(?s)\.(\w+)\s*\(\s*(.*?)\s*\)',txt,flags=re.MULTILINE)
#
if '.*' in txt:
# Parse module definition
mname = re.findall(r'\w+',txt)[0]
filelist = self.view.window().lookup_symbol_in_index(mname)
if not filelist:
return
for f in filelist:
fname = sublimeutil.normalize_fname(f[0])
mi = verilogutil.parse_module_file(fname,mname,no_inst=True)
if mi:
break
if not mi:
return
dot_star = ''
b0 = [x[0] for x in bl]
for p in mi['port']:
if p['name'] not in b0:
dot_star += '.' + p['name']+'('+p['name']+'),\n'
# select the .* and replace it (exclude the two last character which are ',\n')
if dot_star != '' :
r_tmp = self.view.find(r'\.\*',r.a)
self.view.replace(edit,r_tmp,dot_star[:-2])
else : # case where .* was superfluous (all bindings were manual) : remove .* including the potential ,
r_tmp = self.view.find(r'\.\*\s*(,)?',r.a)
self.view.erase(edit,r_tmp)
else:
# Find beginning of the binding and insert the .*
r_begin = self.view.find(r'(\w+|\))\b\s*\w+\s*\(',r.a)
if r.contains(r_begin):
cnt = 0
# erase all binding where port and signal have same name
for b in bl:
if b[0]==b[1]:
cnt = cnt + 1
r_tmp = self.view.find(r'\.'+b[0]+r'\s*\(\s*' + b[0] + r'\s*\)\s*(,)?',r.a)
if r.contains(r_tmp):
self.view.erase(edit,r_tmp)
r_tmp = self.view.full_line(r_tmp.a)
m = re.search(r'^\s*(\/\/.*)?$',self.view.substr(r_tmp))
if m:
self.view.erase(edit,r_tmp)
# Insert .* only if something was removed. Add , if not all binding were removed
if cnt > 0:
if cnt==len(bl):
self.view.insert(edit,r_begin.b,'.*')
else :
self.view.insert(edit,r_begin.b,'.*,')
self.view.run_command("verilog_align")
def lookup_macro(view, name):
txt = ''
params = []
filelist = view.window().lookup_symbol_in_index(name)
if filelist:
fname = view.file_name()
# Check if symbol is defined in current file first
if fname in [sublimeutil.normalize_fname(f[0]) for f in filelist]:
with open(fname, 'r') as f:
flines = str(f.read())
txt, params = verilogutil.get_macro(flines, name)
else:
for fi in filelist:
fname = sublimeutil.normalize_fname(fi[0])
with open(fname, 'r') as f:
flines = str(f.read())
txt, params = verilogutil.get_macro(flines, name)
if txt:
break
return txt, params
def lookup_module(view, mname):
mi = None
filelist = view.window().lookup_symbol_in_index(mname)
if filelist:
# Check if module is defined in current file first
fname = view.file_name()
flist_norm = [sublimeutil.normalize_fname(f[0]) for f in filelist]
if fname in flist_norm:
_, _, rowcol = filelist[flist_norm.index(fname)]
mi = verilogutil.parse_module_file(fname, mname)
if mi:
mi['fname'] = (fname, rowcol[0], rowcol[1])
# Consider first file with a valid module definition to be the correct one
else:
for f in filelist:
fname, display_fname, rowcol = f
fname = sublimeutil.normalize_fname(fname)
mi = verilogutil.parse_module_file(fname, mname)
if mi:
mi['fname'] = (fname, rowcol[0], rowcol[1])
break
# print('[SV:lookup_module] {0}'.format(mi))
return mi
def run(self, edit):
if len(self.view.sel()) == 0: return
r = self.view.sel()[0]
scope = self.view.scope_name(r.a)
if 'meta.module.inst' not in scope:
return
# Select whole module instantiation
r = sublimeutil.expand_to_scope(self.view, 'meta.module.inst', r)
if self.view.classify(r.a) & sublime.CLASS_LINE_START == 0:
r.a = self.view.find_by_class(r.a, False, sublime.CLASS_LINE_START)
# print(self.view.substr(r))
txt = verilogutil.clean_comment(self.view.substr(r))
# Parse module definition
mname = re.findall(r'\w+', txt)[0]
filelist = self.view.window().lookup_symbol_in_index(mname)
if not filelist:
return
for f in filelist:
fname = sublimeutil.normalize_fname(f[0])
mi = verilogutil.parse_module_file(fname, mname, no_inst=True)
if mi:
break
if not mi:
sublime.status_message(
'Unable to retrieve module information for ' + mname)
return
settings = self.view.settings()
mpl = [x['name'] for x in mi['port']]
mpal = [x['name'] for x in mi['param']]
#Extract existing binding
bl = re.findall(r'(?s)\.(\w+)\s*\(\s*(.*?)\s*\)\s*(,|\))',
txt,
flags=re.MULTILINE)
# Handle case of binding by position (TODO: support parameter as well ...)
if not bl:
m = re.search(
r'(?s)(#\s*\((?P<params>.*?)\)\s*)?\s*\w+\s*\((?P<ports>.*?)\)\s*;',
txt,
flags=re.MULTILINE)
pl = m.group('ports')
if pl:
pa = pl.split(',')
bt = ''
for i, p in enumerate(pa):
if i >= len(mpl):
break
bl.append((mpl[i], p.strip()))
bt += '.{portName}({sigName}),\n'.format(
portName=bl[-1][0], sigName=bl[-1][1])
# Replace connection by position by connection by name
r_tmp = self.view.find(pl, r.a, sublime.LITERAL)
if r.contains(r_tmp):
self.view.replace(edit, r_tmp, bt)
# Update region
r = sublimeutil.expand_to_scope(self.view,
'meta.module.inst', r)
ipl = [x[0] for x in bl]
# Check for added port
apl = [x for x in mpl if x not in ipl]
if apl:
(decl, ac, wc) = VerilogDoModuleInstCommand.get_connect(
self, self.view, settings, mi)
last_char = self.view.substr(sublime.Region(r.a, r.b -
2)).strip(' \t')[-1]
b = '\n' if last_char != '\n' else ''
for p in apl:
b += "." + p + "("
if p in ac.keys():
b += ac[p]
else:
b += p
b += "),"
if p in wc.keys():
b += " // TODO: Check connection ! " + wc[p]
b += "\n"
# Add binding at the end of the instantiation
self.view.insert(edit, r.b - 2, b)
# Check for deleted port
dpl = [x for x in ipl if x not in mpl and x not in mpal]
for p in dpl:
r_tmp = self.view.find(r'(?s)\.' + p + r'\s*\(.*?\)\s*(,|\)\s*;)',
r.a)
if r.contains(r_tmp):
s = self.view.substr(r_tmp)
if s[-1] == ';':
s_tmp = s[:-1].strip()[:-1]
r_tmp.b -= (len(s) - len(s_tmp))
self.view.erase(edit, r_tmp)
r_tmp = self.view.full_line(r_tmp.a)
# cleanup comment
m = re.search(r'^\s*(\/\/.*)?$', self.view.substr(r_tmp))
if m:
self.view.erase(edit, r_tmp)
# Print status
# print('[reconnect] Module Port list = ' + str(mpl))
# print('[reconnect] Instance Port list = ' + str(ipl))
# print('[reconnect] => Removed Port list = ' + str(dpl))
# print('[reconnect] => Added Port list = ' + str(apl))
s = ''
if dpl:
s += "Removed %d ports: %s\n" % (len(dpl), str(dpl))
if apl:
s += "Added %d ports: %s\n" % (len(apl), str(apl))
decl_clean = ''
ac_clean = {}
for p in apl:
if p in ac:
ac_clean[p] = ac[p]
m = re.search(r'^.*\b' + p + r'\b.*;', decl, re.MULTILINE)
if m:
decl_clean += m.group(0) + '\n'
for p in ipl:
if p in wc:
wc.pop(p)
nb_decl = len(decl_clean.splitlines())
if decl_clean:
r_start = VerilogDoModuleInstCommand.get_region_decl(
self, self.view, settings, r.a)
self.view.insert(edit, r_start, '\n' + decl_clean)
s += 'Adding ' + str(nb_decl) + ' signal(s) declaration(s)\n'
if len(ac_clean) > 0:
s += 'Non-perfect name match for ' + str(
len(ac_clean)) + ' port(s) : ' + str(ac_clean) + '\n'
if len(wc) > 0:
s += 'Found ' + str(
len(wc)) + ' mismatch(es) for port(s): ' + str(
[x for x in wc.keys()]) + '\n'
if s:
sublimeutil.print_to_panel(s, 'SystemVerilog')
# Realign
self.view.run_command("verilog_align")
