def render_vhdl(self):
y = []
y.append("library IEEE;")
y.append("use IEEE.STD_LOGIC_1164.all;")
y.append(eol())
y.append("entity " + self.name + " is")
y.append("port(")
for i in range(len(self.in_list)):
one_thing = self.in_list[i]
one_str = tab() + one_thing.declare_vhdl()[0]
y.append(one_str)
for i in range(len(self.out_list)):
one_thing = self.out_list[i]
one_str = tab() + one_thing.declare_vhdl()[0]
if i == len(self.out_list) - 1:
one_str = one_str[:-1] + ");"
y.append(one_str)
y.append("end " + self.name + ";")
y.append(eol())
y.append("architecture " + self.name + "_arch of " + self.name + " is")
for i in self.children[0].declare_vhdl():
y.append(tab() + i)
y.append("begin")
for i in self.children[0].render_vhdl():
y.append(tab() + i)
y.append(tab() + one_signal_name(self.name, 0) + " <= d_in;")
for one_tap in self.taps:
y.append(tab() + one_tap_name(one_tap) + " <= " + one_signal_name(self.name, one_tap) + ";")
y.append(tab() + "d_out <= " + one_signal_name(self.name, self.children[0].num_delays) + ";")
y.append("end " + self.name + "_arch;")
return y
def render_vhdl(self):
y = []
y.append("library IEEE;")
y.append("use IEEE.STD_LOGIC_1164.all;")
y.append(eol())
y.append("entity " + self.name + " is")
y.append("port(")
for i in range(len(self.in_list)):
one_thing = self.in_list[i]
one_str = tab() + one_thing.declare_vhdl()[0]
y.append(one_str)
for i in range(len(self.out_list)):
one_thing = self.out_list[i]
one_str = tab() + one_thing.declare_vhdl()[0]
if i == len(self.out_list) - 1:
one_str = one_str[:-1] + ");"
y.append(one_str)
y.append("end " + self.name + ";")
y.append(eol())
y.append("architecture " + self.name + "_arch of " + self.name + " is")
y.append("process(clk)")
y.append("begin")
y.append(tab(1) + "if rising_edge(clk) then")
y.append(tab(2) + "if rst_global = '1' then")
y.append(tab(3) + "q0 <= (others => '0');")
for one_input in self.input_name_list:
y.append(tab(2) + "elsif " + one_input + " = '1' then")
if "set" in one_input:
y.append(tab(3) + "q0(0) <= '1';")
elif "rst" in one_input:
y.append(tab(3) + "q0(0) <= '0';")
elif "tog" in one_input:
y.append(tab(3) + "q0(0) <= not q0(0);")
y.append(tab(2) + "end if; ")
y.append(tab(1) + "end if; ")
y.append("end process;")
y.append("q <= q0;")
y.append("end " + self.name + "_arch;")
return y
def test_basic_delay():
cng = CentralNameGen()
uut = BasicDelay(name="myDelay",
num_delays=8,
clk="clk",
rst="rst",
width=4,
central_name_gen=cng)
for i in uut.declare_vhdl():
print(i)
for i in uut.render_vhdl():
print(i)
print(eol(4))
def wrap_rst_mgr(numel=200, numdrivers=3):
y = []
y.append("library IEEE;")
y.append("use IEEE.std_logic_1164.all;")
y.append("")
y.append("entity rst_mgr is")
y.append("port(")
y.append(tab() + "clock_fast : in std_logic;")
y.append(tab() + "clock_slow : in std_logic;")
y.append(tab() + "reset_in : in std_logic;")
y.append(tab() + "reset_out : out std_logic)")
y.append("end rst_mgr;")
y.append(eol())
y.append("architecture rst_mgr_arch of rst_mgr is")
y.append(tab() + "signal sig_fast : bit_vector(" + str(numel - 1) +
" downto 0);")
y.append(tab() + "signal sig_slow : bit_vector(" + str(numel - 1) +
" downto 0);")
y.append("begin")
y.append(eol())
# Create fast clock process:
y.append("process(clock_fast)")
y.append("begin")
y.append(tab() + "if rising_edge(clock_fast) then")
y.extend([
tab(2) + i
for i in assign_fast_signals(numel=numel, num_drivers=numdrivers)
])
y.append(tab() + "end if;")
y.append("end process;")
y.append(eol())
# Create slow clock process:
y.append("process(clock_slow)")
y.append("begin")
y.append(tab() + "if rising_edge(clock_slow) then")
y.extend([
tab(2) + i
for i in assign_slow_signals(numel=numel, num_drivers=numdrivers)
])
y.append(tab() + "end if;")
y.append("end process;")
y.append(eol())
y.extend(assign_output(numel=numel, num_drivers=numdrivers))
y.append(eol())
y.append("end rst_mgr_arch;")
y.append(eol())
return y
def render_module_vhdl(self):
"""Includes entity declaration"""
if self.favor_fast_sim:
the_datatype = self.fast_datatype
else:
the_datatype = self.accurate_datatype
y = []
y.append("library IEEE;")
y.append("use IEEE.std_logic_1164.all;")
y.append(eol())
y.append("entity " + self.module_name + " is")
i = 0
if len(self.generics) > 0:
y.append(tab() + "generic(")
for one_generic in self.generics:
one_str = tab(
2) + one_generic.name + " : " + one_generic.datatype
one_str += ("_vector(" + str(one_generic.width-1) + " downto 0)") if \
(one_generic.datatype in synthesizable_types) else ""
one_str += ";" if i < len(self.generics) - 1 else ");"
y.append(one_str)
i += 1
y.append(tab() + "port(")
i = 0
for one_input in self.inputs:
one_str = tab(2) + one_input.name + " : in " + the_datatype + "_vector(" + \
str(one_input.width-1) + " downto 0);"
# one_str += ";" if i < len(self.inputs)-1 else ");"
y.append(one_str)
i += 1
i = 0
for one_output in self.outputs:
one_str = tab(2) + one_output.name + " : out " + the_datatype + "_vector(" + \
str(one_input.width - 1) + " downto 0)"
one_str += ";" if i < len(self.inputs) - 1 else ");"
y.append(one_str)
i += 1
y.append("end " + self.module_name + ";")
y.append(eol())
y.append("architecture " + self.module_name + "_arch of " +
self.module_name + " is")
for one_child in self.child_modules:
y.extend([
tab() + i
for i in one_child.render_component_declaration_vhdl()
])
y.append(eol())
for one_signal in self.signals:
y.append(tab() + "signal " + one_signal.name + " : " +
the_datatype + "_vector(" + str(one_signal.width - 1) +
" downto 0);")
y.append(eol())
y.append("begin")
y.append(eol())
for one_clk in self.clocks:
if one_clk != "__async__":
y.append("process(" + one_clk + ")")
y.append("begin")
y.append(tab() + "if rising_edge(" + one_clk + ") then")
y.append(tab(2) + "if " + self.global_rst + " = '1' then")
for one_signal in self.signals:
if one_clk == self.clocks_by_name[one_signal.name]:
y.append(
tab(3) + one_signal.name + " <= (others => '0');")
y.append(tab(2) + "else")
for one_signal in self.signals:
if one_clk == self.clocks_by_name[one_signal.name]:
y.append(
tab(3) + one_signal.name + " <= " +
self.expressions_by_name[one_signal.name] + ";")
y.append(tab(2) + "end if;")
y.append(tab() + "end if;")
y.append("end process;")
y.append(eol())
for one_port_map in self.port_maps:
y.extend(one_port_map.render_vhdl())
y.append(eol())
for one_signal in self.outputs:
y.append(one_signal.name + " <= " +
self.expressions_by_name[one_signal.name] + ";")
y.append(eol())
y.append("end " + self.module_name + "_arch;")
y.append(eol())
y.append(eol())
return y
tab(2) + i
for i in assign_fast_signals(numel=numel, num_drivers=numdrivers)
])
y.append(tab() + "end if;")
y.append("end process;")
y.append(eol())
# Create slow clock process:
y.append("process(clock_slow)")
y.append("begin")
y.append(tab() + "if rising_edge(clock_slow) then")
y.extend([
tab(2) + i
for i in assign_slow_signals(numel=numel, num_drivers=numdrivers)
])
y.append(tab() + "end if;")
y.append("end process;")
y.append(eol())
y.extend(assign_output(numel=numel, num_drivers=numdrivers))
y.append(eol())
y.append("end rst_mgr_arch;")
y.append(eol())
return y
if __name__ == "__main__":
with open("./vhdl_generated/reset_module.vhd", 'w') as f:
for line in wrap_rst_mgr():
f.write(line)
f.write(eol())