def test_canvas_three():
def _helper(c):
c.addWire(c.m1, 'a', None, 1, (1, -1), (6, 1))
c.addWire(c.m3, 'a', None, 2, (1, -1), (6, 1))
c.addWire(c.m5, 'a', None, 3, (1, -1), (6, 1))
c.addWire(c.m2, 'a', None, 1, (1, -1), (3, 1))
c.addWire(c.m4, 'a', None, 2, (1, -1), (3, 1))
c.addWire(c.m6, 'a', None, 3, (1, -1), (3, 1))
c.addVia(c.v1, 'a', None, 1, 1)
c.addVia(c.v2, 'a', None, 2, 1)
c.addVia(c.v3, 'a', None, 2, 2)
c.addVia(c.v4, 'a', None, 3, 2)
c.addVia(c.v5, 'a', None, 3, 3)
c.computeBbox()
c1 = CanvasPDK()
_helper(c1)
c1.gen_data(run_drc=True)
assert c1.drc.num_errors == 0
c2 = DefaultCanvas(Pdk().load(layers_json))
_helper(c2)
c2.gen_data(run_drc=True)
assert c2.drc.num_errors == 0
export_to_viewer("test_canvas_3_c1", c1)
export_to_viewer("test_canvas_3_c2", c2)
d1 = {'bbox': c1.bbox.toList(), 'globalRoutes': [], 'globalRouteGrid': [], 'terminals': c1.removeDuplicates(allow_opens=True)}
d2 = {'bbox': c2.bbox.toList(), 'globalRoutes': [], 'globalRouteGrid': [], 'terminals': c2.removeDuplicates(allow_opens=True)}
assert d1 == d2
def test_donotroute():
name = f'ckt_{get_test_id()}'
netlist = textwrap.dedent(f"""\
.subckt inv vi vo vccx vssx
mp0 vo vi vccx vccx p w=360e-9 m=1 nf=2
mn0 vo vi vssx vssx n w=360e-9 m=1 nf=2
.ends
.subckt {name} vi vo vccx vssx
xi0 vi v1 vccx vssx inv
xi1 v1 vo vccx vssx inv
.ends
""")
constraints = [{
"constraint": "AutoConstraint",
"isTrue": False
}, {
"constraint": "PowerPorts",
"ports": ["vccx"]
}, {
"constraint": "GroundPorts",
"ports": ["vssx"]
}, {
"constraint": "DoNotRoute",
"nets": ["v1", "vccx", "vssx"]
}]
example = build_example(name, netlist, constraints)
_, run_dir = run_example(example, cleanup=False)
# There should be opens in the generated layout
with (run_dir / '3_pnr' / f'{name.upper()}_0.json').open('rt') as fp:
d = json.load(fp)
cv = CanvasPDK()
cv.terminals = d['terminals']
cv.removeDuplicates()
assert len(cv.rd.opens) > 0, 'Layout should have opens'
# The generated and loaded files should be identical
input_dir = run_dir / '3_pnr' / 'inputs'
verilog_d = VerilogJsonTop.parse_file(input_dir /
f'{name.upper()}.verilog.json')
constraint_files_l, pnr_const_ds_l = load_constraint_files(input_dir)
constraint_files_g, pnr_const_ds_g = gen_constraint_files(
verilog_d, input_dir)
assert constraint_files_l == constraint_files_g
assert pnr_const_ds_l == pnr_const_ds_g
def test_zero():
cv = CanvasPDK()
ox = oy = 0
track_pattern = {'G': [6], 'S': [4], 'D': [2]}
for nfin in range(1, 9):
ox = 0
for model_name in ['n', 'p']:
for device_type in ["stack", "parallel"]:
for nf in [2, 4, 6]:
mg = MOS()
tx = Transistor(model_name=model_name,
nf=nf,
nfin=nfin,
device_type=device_type)
data = mg.mos(tx, track_pattern=track_pattern)
place(cv, data, ox, oy)
ox += data['bbox'][2]
oy += data['bbox'][3]
compare_with_golden("test_transistor_0", cv)
def test_canvas_two():
c1 = CanvasPDK()
c1.addWire(c1.m1, 'a', None, 1, (1, -1), (6, 1))
c1.addWire(c1.m2, 'a', None, 1, (1, -1), (3, 1))
c1.addVia(c1.v1, 'a', None, 1, 1)
c1.computeBbox()
c1.gen_data(run_drc=True)
assert c1.drc.num_errors == 0
c1 = CanvasPDK()
c1.addWire(c1.m1, 'a', None, 1, (1, -1), (6, 1))
c1.addWire(c1.m1, 'a', None, 2, (1, -1), (6, 1))
c1.addWire(c1.m2, 'a', None, 1, (1, -1), (3, 1))
c1.addVia(c1.v1, 'a', None, 1, 1)
c1.addVia(c1.v1, 'a', None, 2, 1)
c1.computeBbox()
c1.gen_data(run_drc=True)
assert c1.drc.num_errors == 1, f'horizontal via spacing'
c1 = CanvasPDK() # vertical via spacing
c1.addWire(c1.m2, 'a', None, 1, (1, -1), (3, 1))
c1.addWire(c1.m2, 'a', None, 2, (1, -1), (3, 1))
c1.addWire(c1.m3, 'a', None, 1, (1, -1), (6, 1))
c1.addVia(c1.v2, 'a', None, 1, 1)
c1.addVia(c1.v2, 'a', None, 1, 2)
c1.computeBbox()
c1.gen_data(run_drc=True)
assert c1.drc.num_errors == 1, f'vertical via spacing'
def test_canvas_one():
c = CanvasPDK()
for x in range(1, 4):
c.addWire(c.m1, 'a', None, x, (1, -1), (6, 1))
c.addWire(c.m3, 'a', None, x, (1, -1), (6, 1))
c.addWire(c.m5, 'a', None, x, (1, -1), (6, 1))
for y in range(0, 8):
c.addWire(c.m2, 'a', None, y, (1, -1), (3, 1))
c.addWire(c.m4, 'a', None, y, (1, -1), (3, 1))
c.addWire(c.m6, 'a', None, y, (1, -1), (3, 1))
c.addVia(c.v1, 'a', None, 1, 1)
c.addVia(c.v2, 'a', None, 1, 2)
c.addVia(c.v3, 'a', None, 1, 3)
c.addVia(c.v4, 'a', None, 1, 4)
c.addVia(c.v5, 'a', None, 1, 5)
compare_with_golden("test_canvas_1", c)
def test_canvas_zero():
c = CanvasPDK()
print(c)