def libnative_libfuncs_open_library_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() # setup open func def open_func(op, pc): # return my seglist cpu.w_reg(REG_D0, 0xcafebabe) trap_id = traps.setup(open_func, auto_rts=True) exp_addr = lib.get_addr() - 6 mem.w16(exp_addr, trap_id | 0xa000) # add lib lf = LibFuncs(machine, alloc) lib_base = lf.open_library(lib.get_addr(), run_sp=sp) assert lib_base == 0xcafebabe # cleanup lib.free() assert alloc.is_all_free()
def libnative_libfuncs_set_function_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib_addr = lib.get_addr() lib.setup() lib.fill_funcs(op_jmp, 0xcafebabe) assert lib.neg_size == 36 # patch function lvo = -30 addr = lib.get_addr() + lvo assert mem.r16(addr) == op_jmp assert mem.r32(addr+2) == 0xcafebabe lf = LibFuncs(machine, alloc) old_addr = lf.set_function(lib_addr, lvo, 0xdeadbeef) assert old_addr == 0xcafebabe assert mem.r16(addr) == op_jmp assert mem.r32(addr+2) == 0xdeadbeef assert lib.check_sum() # invalid function old_addr = lf.set_function(lib_addr, -36, 0) assert old_addr is None # cleanup lib.free() assert alloc.is_all_free()
def libnative_libfuncs_set_function_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib_addr = lib.get_addr() lib.setup() lib.fill_funcs(op_jmp, 0xcafebabe) assert lib.neg_size == 36 # patch function lvo = -30 addr = lib.get_addr() + lvo assert mem.r16(addr) == op_jmp assert mem.r32(addr + 2) == 0xcafebabe lf = LibFuncs(machine, alloc) old_addr = lf.set_function(lib_addr, lvo, 0xdeadbeef) assert old_addr == 0xcafebabe assert mem.r16(addr) == op_jmp assert mem.r32(addr + 2) == 0xdeadbeef assert lib.check_sum() # invalid function old_addr = lf.set_function(lib_addr, -36, 0) assert old_addr is None # cleanup lib.free() assert alloc.is_all_free()
def create_machine(cpu_type=Machine.CPU_TYPE_68000): m = Machine(cpu_type, raise_on_main_run=False) cpu = m.get_cpu() mem = m.get_mem() code = m.get_ram_begin() stack = m.get_scratch_top() return m, cpu, mem, code, stack
def libnative_libfuncs_close_library_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) segloader = SegmentLoader(alloc) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() # setup seglist seglist = SegList.alloc(alloc, [64]) segloader.register_seglist(seglist.get_baddr()) # setup expunge func def close_func(op, pc): # return my seglist cpu.w_reg(REG_D0, seglist.get_baddr()) trap_id = traps.setup(close_func, auto_rts=True) exp_addr = lib.get_addr() - 12 mem.w16(exp_addr, trap_id | 0xa000) # add lib lf = LibFuncs(machine, alloc) sl = lf.close_library(lib.get_addr(), segloader, run_sp=sp) assert seglist.get_baddr() == sl # cleanup lib.free() assert alloc.is_all_free() assert segloader.shutdown() == 0
def libnative_initres_init_test(buildlibnix): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() alloc = MemoryAlloc.for_machine(machine) init_addr = machine.get_ram_begin() - 4 sp = init_addr - 4 # load lib seglist, addr, size, end = load_lib(alloc, buildlibnix) # setup init func def init_func(op, pc): assert cpu.r_reg(REG_A0) == seglist.get_baddr() # return my lib_base cpu.w_reg(REG_D0, 0xcafebabe) trap_id = traps.setup(init_func, auto_rts=True) mem.w16(init_addr, trap_id | 0xa000) # build fake resident res = Resident.alloc(alloc, "bla.library", "blub") res.setup(flags=0, version=42, type=NodeType.NT_LIBRARY, pri=-7, init=init_addr) # init resident ir = InitRes(machine, alloc) lib_base, mem_obj = ir.init_resident( res.get_addr(), seglist.get_baddr(), run_sp=sp) assert lib_base == 0xcafebabe assert mem_obj is None seglist.free() res.free() traps.free(trap_id) assert alloc.is_all_free()
def libnative_libfuncs_add_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # setup exec lib exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 36) exec_lib.setup() mem.w32(4, exec_lib.get_addr()) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() mem.w32(lib.get_addr()-36, 0xdeadbeef) # check lib sum assert lib.sum == 0 # add lib lf = LibFuncs(machine, alloc) lf.add_library(lib.get_addr()) # check that lib was added assert len(exec_lib.lib_list) == 1 assert [a for a in exec_lib.lib_list] == [lib] assert lib.sum == 0xdeadbeef assert lf.find_library("my.library") == lib.get_addr() # cleanup lib.free() exec_lib.free() assert alloc.is_all_free()
def libnative_libfuncs_add_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # setup exec lib exec_lib = ExecLibrary.alloc(alloc, name="exec.library", id_string="bla", neg_size=36) assert exec_lib.LibNode.neg_size.val == 36 assert exec_lib.LibNode.pos_size.val == ExecLibrary.get_size() exec_lib.new_lib() mem.w32(4, exec_lib.get_addr()) # new lib lib = Library.alloc(alloc, name="my.library", id_string="bla", neg_size=36) assert lib.neg_size.val == 36 lib.new_lib() mem.w32(lib.get_addr() - 36, 0xDEADBEEF) # check initial lib sum assert lib.sum.val == 0 assert lib.calc_sum() == 0xDEADBEEF # add lib lf = LibFuncs(machine, alloc) lf.add_library(lib.addr) # check that lib was added assert len(exec_lib.lib_list) == 1 libs = [a for a in exec_lib.lib_list] assert list(map(lambda x: x.addr, libs)) == [lib.addr] # check that libsum was calced assert lib.sum.val == 0xDEADBEEF assert lf.find_library("my.library") == lib.addr # cleanup lib.free() exec_lib.free() assert alloc.is_all_free()
def libnative_libfuncs_add_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # setup exec lib exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 36) exec_lib.setup() mem.w32(4, exec_lib.get_addr()) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() mem.w32(lib.get_addr() - 36, 0xDEADBEEF) # check lib sum assert lib.sum == 0 # add lib lf = LibFuncs(machine, alloc) lf.add_library(lib.get_addr()) # check that lib was added assert len(exec_lib.lib_list) == 1 assert [a for a in exec_lib.lib_list] == [lib] assert lib.sum == 0xDEADBEEF assert lf.find_library("my.library") == lib.get_addr() # cleanup lib.free() exec_lib.free() assert alloc.is_all_free()
def libnative_libfuncs_set_function_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, name="my.library", id_string="bla", neg_size=36) lib_addr = lib.get_addr() lib.new_lib() lib.fill_funcs(op_jmp, 0xCAFEBABE) assert lib.neg_size.val == 36 # patch function lvo = -30 addr = lib.get_addr() + lvo assert mem.r16(addr) == op_jmp assert mem.r32(addr + 2) == 0xCAFEBABE lf = LibFuncs(machine, alloc) old_addr = lf.set_function(lib_addr, lvo, 0xDEADBEEF) assert old_addr == 0xCAFEBABE assert mem.r16(addr) == op_jmp assert mem.r32(addr + 2) == 0xDEADBEEF assert lib.check_sum() # invalid function old_addr = lf.set_function(lib_addr, -36, 0) assert old_addr is None # cleanup lib.free() assert alloc.is_all_free()
def machine_hwaccess_ignore_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, 'ignore') assert mem.cpu_r8(0xbf0000) == 0 mem.cpu_w8(0xbf0000, 42) assert mem.cpu_r16(0xdf0000) == 0 mem.cpu_w16(0xdf0000, 0xdead) assert caplog.record_tuples == [ ('hw', logging.WARN, 'CIA read byte @bf0000'), ('hw', logging.WARN, 'CIA write byte @bf0000: 2a'), ('hw', logging.WARN, 'Custom Chip read word @df0000'), ('hw', logging.WARN, 'Custom Chip write word @df0000: dead')]
def setup(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) sp = machine.get_ram_begin() - 4 # setup exec exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 520*6) exec_lib.setup() exec_lib.fill_funcs() exec_base = exec_lib.get_addr() mem.w32(4, exec_base) machine.set_zero_mem(0, exec_base) return machine, alloc, sp, mem, exec_lib
def machine_hwaccess_ignore_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, 'ignore') assert mem.cpu_r8(0xbf0000) == 0 mem.cpu_w8(0xbf0000, 42) assert mem.cpu_r16(0xdf0000) == 0 mem.cpu_w16(0xdf0000, 0xdead) assert caplog.record_tuples == [ ('hw', logging.WARN, 'CIA read byte @bf0000'), ('hw', logging.WARN, 'CIA write byte @bf0000: 2a'), ('hw', logging.WARN, 'Custom Chip read word @df0000'), ('hw', logging.WARN, 'Custom Chip write word @df0000: dead') ]
def machine_hwaccess_ignore_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, "ignore") assert mem.cpu_r8(0xBF0000) == 0 mem.cpu_w8(0xBF0000, 42) assert mem.cpu_r16(0xDF0000) == 0 mem.cpu_w16(0xDF0000, 0xDEAD) assert caplog.record_tuples == [ ("hw", logging.WARN, "CIA read byte @bf0000"), ("hw", logging.WARN, "CIA write byte @bf0000: 2a"), ("hw", logging.WARN, "Custom Chip read word @df0000"), ("hw", logging.WARN, "Custom Chip write word @df0000: dead"), ]
def libnative_libfuncs_sum_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() mem.w32(lib.get_addr() - 36, 0xdeadbeef) # sum lib lf = LibFuncs(machine, alloc) lf.sum_library(lib.get_addr()) assert lib.sum == 0xdeadbeef # cleanup lib.free() assert alloc.is_all_free()
def setup(path_mgr=None): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) segload = SegmentLoader(alloc, path_mgr=path_mgr) loader = LibLoader(machine, alloc, segload) sp = machine.get_ram_begin() - 4 # setup exec exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 520*6) exec_lib.setup() exec_lib.fill_funcs() exec_base = exec_lib.get_addr() mem.w32(4, exec_base) machine.set_zero_mem(0, exec_base) return loader, segload, alloc, mem, sp, exec_lib
def libnative_libfuncs_sum_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, name="my.library", id_string="bla", neg_size=36) lib.new_lib() mem.w32(lib.get_addr() - 36, 0xDEADBEEF) # sum lib lf = LibFuncs(machine, alloc) lf.sum_library(lib.get_addr()) assert lib.sum.val == 0xDEADBEEF # cleanup lib.free() assert alloc.is_all_free()
def libnative_libfuncs_sum_library_test(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, "my.library", "bla", 36) lib.setup() mem.w32(lib.get_addr() - 36, 0xDEADBEEF) # sum lib lf = LibFuncs(machine, alloc) lf.sum_library(lib.get_addr()) assert lib.sum == 0xDEADBEEF # cleanup lib.free() assert alloc.is_all_free()
def libnative_makelib_test(): machine = Machine() mem = machine.get_mem() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # build lib info in memory vectors = 0x100 mem.w32(vectors, 0x400) mem.w32(vectors + 4, 0x600) mem.w32(vectors + 8, 0x800) mem.w32(vectors + 12, 0xFFFFFFFF) name_addr = 0x1F0 mem.w_cstr(name_addr, "bla.library") init_tab = 0x200 ib = InitStructBuilder(mem, init_tab) name_off = LibraryStruct.get_field_offset_for_path("lib_Node.ln_Name") ib.init_long(name_off, name_addr) ib.end() init_func = 0x300 mem.w16(init_func, op_rts) pos_size = LibraryStruct.get_size() # make library ml = MakeLib(machine, alloc) lib_base, mem_obj = ml.make_library(vectors, init_tab, init_func, pos_size, 0, run_sp=sp) assert lib_base != 0 # check library lib = Library(mem, lib_base) assert lib.get_name() == "bla.library" assert lib.get_pos_size() == 36 assert lib.get_neg_size() == 20 # round_long(3*6) assert mem.r32(lib_base - 4) == 0x400 assert mem.r32(lib_base - 10) == 0x600 assert mem.r32(lib_base - 16) == 0x800 # cleanup alloc.free_memory(mem_obj) assert alloc.is_all_free()
def machine_disasm_default_test(): mach = Machine() disasm = DisAsm(mach) mem = mach.get_mem() cpu = mach.get_cpu() traps = mach.get_traps() # trap without func mem.w16(0, 0xa123) assert disasm.disassemble(0) == (2, "PyTrap #$123") # trap with func def bla(opcode, pc): pass tid = traps.setup(bla) mem.w16(2, 0xa000 | tid) assert disasm.disassemble(2) == (2, "PyTrap #$%03x ; bla" % tid) traps.free(tid)
def machine_disasm_block_test(): mach = Machine() disasm = DisAsm(mach) buf = b"\x4e\x75" + b"\x10\x1c" + b"\x48\xe7\x3f\x3e" assert disasm.disassemble_block(buf, 0x100) == [ (0x100, [0x4e75], "rts"), (0x102, [0x101c], "move.b (A4)+, D0"), (0x104, [0x48e7, 0x3f3e], "movem.l D2-D7/A2-A6, -(A7)") ]
def machine_hwaccess_abort_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, 'abort') with pytest.raises(HWAccessError): mem.cpu_r8(0xbf0000) with pytest.raises(HWAccessError): mem.cpu_w8(0xbf0000, 42) with pytest.raises(HWAccessError): mem.cpu_r16(0xdf0000) with pytest.raises(HWAccessError): mem.cpu_w16(0xdf0000, 0xdead) assert caplog.record_tuples == [ ('hw', logging.WARN, 'CIA read byte @bf0000'), ('hw', logging.WARN, 'CIA write byte @bf0000: 2a'), ('hw', logging.WARN, 'Custom Chip read word @df0000'), ('hw', logging.WARN, 'Custom Chip write word @df0000: dead')]
def libnative_makelib_test(): machine = Machine() mem = machine.get_mem() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # build lib info in memory vectors = 0x100 mem.w32(vectors, 0x400) mem.w32(vectors+4, 0x600) mem.w32(vectors+8, 0x800) mem.w32(vectors+12, 0xffffffff) name_addr = 0x1f0 mem.w_cstr(name_addr, "bla.library") init_tab = 0x200 ib = InitStructBuilder(mem, init_tab) name_off = LibraryStruct.get_field_offset_for_path("lib_Node.ln_Name") ib.init_long(name_off, name_addr) ib.end() init_func = 0x300 mem.w16(init_func, op_rts) pos_size = LibraryStruct.get_size() # make library ml = MakeLib(machine, alloc) lib_base, mem_obj = ml.make_library( vectors, init_tab, init_func, pos_size, 0, run_sp=sp) assert lib_base != 0 # check library lib = Library(mem, lib_base) assert lib.get_name() == "bla.library" assert lib.get_pos_size() == 36 assert lib.get_neg_size() == 20 # round_long(3*6) assert mem.r32(lib_base - 4) == 0x400 assert mem.r32(lib_base - 10) == 0x600 assert mem.r32(lib_base - 16) == 0x800 # cleanup alloc.free_memory(mem_obj) assert alloc.is_all_free()
def libnative_initres_autoinit_test(buildlibnix): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() alloc = MemoryAlloc.for_machine(machine) init_addr = machine.get_ram_begin() - 4 sp = init_addr - 4 # load lib seglist, addr, size, end = load_lib(alloc, buildlibnix) # setup init func def init_func(op, pc): assert cpu.r_reg(REG_A0) == seglist.get_baddr() trap_id = traps.setup(init_func, auto_rts=True) mem.w16(init_addr, trap_id | 0xa000) # fake vectors vectors = 0x100 mem.w32(vectors, 0x400) mem.w32(vectors+4, 0x600) mem.w32(vectors+8, 0x800) mem.w32(vectors+12, 0xffffffff) # build fake resident res = Resident.alloc(alloc, "bla.library", "blub") res.setup(flags=ResidentFlags.RTF_AUTOINIT, version=42, type=NodeType.NT_LIBRARY, pri=-7) auto_init = AutoInit.alloc(alloc) auto_init.setup(functions=vectors, init_func=init_addr) res.set_auto_init(auto_init) # setup exec lib exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 36) exec_lib.setup() mem.w32(4, exec_lib.get_addr()) # init resident ir = InitRes(machine, alloc) lib_base, mem_obj = ir.init_resident( res.get_addr(), seglist.get_baddr(), run_sp=sp, exec_lib=exec_lib) assert lib_base assert mem_obj seglist.free() res.free() auto_init.free() alloc.free_memory(mem_obj) exec_lib.free() traps.free(trap_id) assert alloc.is_all_free()
def machine_hwaccess_abort_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, 'abort') with pytest.raises(HWAccessError): mem.cpu_r8(0xbf0000) with pytest.raises(HWAccessError): mem.cpu_w8(0xbf0000, 42) with pytest.raises(HWAccessError): mem.cpu_r16(0xdf0000) with pytest.raises(HWAccessError): mem.cpu_w16(0xdf0000, 0xdead) assert caplog.record_tuples == [ ('hw', logging.WARN, 'CIA read byte @bf0000'), ('hw', logging.WARN, 'CIA write byte @bf0000: 2a'), ('hw', logging.WARN, 'Custom Chip read word @df0000'), ('hw', logging.WARN, 'Custom Chip write word @df0000: dead') ]
def machine_memmap_parse_config_test(): machine = Machine() mm = MemoryMap(machine) old_base = mm.get_old_dos_guard_base() cfg = ConfigDict({"hw_access": "ignore", "old_dos_guard": True}) assert mm.parse_config(cfg) assert mm.get_old_dos_guard_base() != old_base assert mm.get_hw_access().mode == HWAccess.MODE_IGNORE assert mm.get_alloc()
def machine_hwaccess_abort_test(caplog): machine = Machine() mem = machine.get_mem() hw = HWAccess.from_mode_str(machine, "abort") with pytest.raises(HWAccessError): mem.cpu_r8(0xBF0000) with pytest.raises(HWAccessError): mem.cpu_w8(0xBF0000, 42) with pytest.raises(HWAccessError): mem.cpu_r16(0xDF0000) with pytest.raises(HWAccessError): mem.cpu_w16(0xDF0000, 0xDEAD) assert caplog.record_tuples == [ ("hw", logging.WARN, "CIA read byte @bf0000"), ("hw", logging.WARN, "CIA write byte @bf0000: 2a"), ("hw", logging.WARN, "Custom Chip read word @df0000"), ("hw", logging.WARN, "Custom Chip write word @df0000: dead"), ]
def machine_hwaccess_create_test(): machine = Machine() # disabled assert HWAccess.from_mode_str(machine, 'disable') is None # valid modes for mode in ('emu', 'abort', 'ignore'): assert HWAccess.from_mode_str(machine, mode) # unknown mode with pytest.raises(ValueError): HWAccess.from_mode_str(machine, 'bla')
def machine_disasm_default_test(): mach = Machine() disasm = DisAsm(mach) mem = mach.get_mem() cpu = mach.get_cpu() traps = mach.get_traps() # trap without func mem.w16(0, 0xa123) assert disasm.disassemble(0) == (2, "PyTrap #$123") # trap with func def bla(opcode, pc): pass tid = traps.setup(bla) mem.w16(2, 0xa000 | tid) assert disasm.disassemble(2) == (2, "PyTrap #$%03x ; bla" % tid) traps.free(tid)
def machine_hwaccess_create_test(): machine = Machine() # disabled assert HWAccess.from_mode_str(machine, "disable") is None # valid modes for mode in ("emu", "abort", "ignore"): assert HWAccess.from_mode_str(machine, mode) # unknown mode with pytest.raises(ValueError): HWAccess.from_mode_str(machine, "bla")
def mem_alloc(request): from amitools.vamos.machine import Machine, MockMemory from amitools.vamos.mem import MemoryAlloc from amitools.vamos.label import LabelManager n = request.param if n == 'mach': m = Machine(use_labels=False) mem = m.get_mem() return mem, MemoryAlloc(mem) elif n == 'mach-label': m = Machine() mem = m.get_mem() return mem, MemoryAlloc(mem, label_mgr=m.get_label_mgr()) elif n == 'mock': mem = MockMemory(fill=23) return mem, MemoryAlloc(mem) else: mem = MockMemory(fill=23) lm = LabelManager() return mem, MemoryAlloc(mem, label_mgr=lm)
def libmgr_setup_default_test(): machine = Machine() mem_map = MemoryMap(machine) mem_map.setup_ram_allocator() scheduler = Scheduler(machine) path_mgr = PathManager() slm = SetupLibManager(machine, mem_map, scheduler, path_mgr) slm.setup() slm.open_base_libs() slm.close_base_libs() slm.cleanup()
def machine_disasm_raw_test(): mach = Machine() disasm = DisAsm(mach) buf = b"\x4e\x75" assert disasm.disassemble_raw(0, buf) == (2, "rts") buf = b"\x10\x1c" assert disasm.disassemble_raw(0, buf) == (2, "move.b (A4)+, D0") buf = b"\x48\xe7\x3f\x3e" assert disasm.disassemble_raw(0, buf) == (4, "movem.l D2-D7/A2-A6, -(A7)") # too short buffer buf = b"\x48\xe7" assert disasm.disassemble_raw(0, buf) == (0, "")
def create_machine(cpu_type=Machine.CPU_TYPE_68000): m = Machine(cpu_type, raise_on_main_run=False) cpu = m.get_cpu() mem = m.get_mem() code = m.get_ram_begin() stack = m.get_scratch_top() return m, cpu, mem, code, stack
def libnative_libfuncs_open_library_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) # new lib lib = Library.alloc(alloc, name="my.library", id_string="bla", neg_size=36) lib.new_lib() # setup open func def open_func(op, pc): # return my seglist cpu.w_reg(REG_D0, 0xCAFEBABE) trap_id = traps.setup(open_func, auto_rts=True) exp_addr = lib.get_addr() - 6 mem.w16(exp_addr, trap_id | 0xA000) # add lib lf = LibFuncs(machine, alloc) lib_base = lf.open_library(lib.get_addr(), run_sp=sp) assert lib_base == 0xCAFEBABE # cleanup lib.free() assert alloc.is_all_free()
def libnative_libfuncs_close_library_test(): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) segloader = SegmentLoader(alloc) # new lib lib = Library.alloc(alloc, name="my.library", id_string="bla", neg_size=36) lib.new_lib() # setup seglist seglist = SegList.alloc(alloc, [64]) segloader.register_seglist(seglist.get_baddr()) # setup expunge func def close_func(op, pc): # return my seglist cpu.w_reg(REG_D0, seglist.get_baddr()) trap_id = traps.setup(close_func, auto_rts=True) exp_addr = lib.get_addr() - 12 mem.w16(exp_addr, trap_id | 0xA000) # add lib lf = LibFuncs(machine, alloc) sl = lf.close_library(lib.get_addr(), segloader, run_sp=sp) assert seglist.get_baddr() == sl # cleanup lib.free() assert alloc.is_all_free() assert segloader.shutdown() == 0
def create_machine(): m = Machine(Machine.CPU_TYPE_68000, raise_on_main_run=False) cpu = m.get_cpu() mem = m.get_mem() traps = m.get_traps() code = m.get_ram_begin() stack = code + 0x1000 return m, cpu, mem, traps, code, stack
def setup(profiler_cfg=None): machine = Machine() alloc = MemoryAlloc(machine.get_mem(), machine.get_ram_begin()) mgr = VLibManager(machine, alloc, profiler_cfg=profiler_cfg) # setup ctx map cpu = machine.get_cpu() mem = machine.get_mem() cpu_type = machine.get_cpu_type() segloader = SegmentLoader(alloc) exec_ctx = ExecLibCtx(machine, alloc, segloader, None) mgr.add_ctx('exec.library', exec_ctx) return machine, alloc, mgr
def setup(path_mgr=None): log_libmgr.setLevel(logging.INFO) log_exec.setLevel(logging.INFO) machine = Machine() # machine.show_instr(True) sp = machine.get_ram_begin() - 4 alloc = MemoryAlloc.for_machine(machine) segloader = SegmentLoader(alloc, path_mgr) cfg = LibMgrCfg() mgr = LibManager(machine, alloc, segloader, cfg) # setup ctx map cpu = machine.get_cpu() mem = machine.get_mem() cpu_type = machine.get_cpu_type() exec_ctx = ExecLibCtx(machine, alloc, segloader, path_mgr) mgr.add_ctx('exec.library', exec_ctx) mgr.add_impl_cls('exec.library', ExecLibrary) dos_ctx = DosLibCtx(machine, alloc, segloader, path_mgr, None, None) mgr.add_ctx('dos.library', dos_ctx) mgr.add_impl_cls('dos.library', DosLibrary) mgr.add_impl_cls('vamostest.library', VamosTestLibrary) mgr.add_impl_cls('vamostestdev.device', VamosTestDevice) return machine, alloc, mgr, sp, cfg
def libmgr_setup_default_test(): machine = Machine() mem_map = MemoryMap(machine) mem_map.setup_ram_allocator() path_mgr = PathManager() slm = SetupLibManager(machine, mem_map, path_mgr) vamos_legacy = ConfigDict({ 'run_command': None, 'start_sub_process': None }) slm.setup(vamos_legacy) slm.open_base_libs() slm.close_base_libs() slm.cleanup()
def machine_disasm_line_test(): mach = Machine() disasm = DisAsm(mach) buf = b"\x4e\x75" assert disasm.disassemble_line(0x100, buf) == (0x100, [0x4e75], "rts") buf = b"\x10\x1c" assert disasm.disassemble_line(0x200, buf) == (0x200, [0x101c], "move.b (A4)+, D0") buf = b"\x48\xe7\x3f\x3e" assert disasm.disassemble_line(0x300, buf) == (0x300, [0x48e7, 0x3f3e], "movem.l D2-D7/A2-A6, -(A7)") # too short buffer buf = b"\x48\xe7" assert disasm.disassemble_line(0, buf) == (0, [], "")
def machine_machine_cfg_test(): cfg = ConfigDict({ 'cpu': '68020', 'ram_size': 2048, 'max_cycles': 128, 'cycles_per_run': 2000 }) m = Machine.from_cfg(cfg, True) assert m assert m.get_cpu_type() == Machine.CPU_TYPE_68020 assert m.get_cpu_name() == '68020' assert m.get_ram_total_kib() == 2048 assert m.max_cycles == 128 assert m.cycles_per_run == 2000 assert m.get_label_mgr()
def machine_machine_cfg_test(): cfg = ConfigDict({ "cpu": "68020", "ram_size": 2048, "max_cycles": 128, "cycles_per_run": 2000 }) m = Machine.from_cfg(cfg, True) assert m assert m.get_cpu_type() == Machine.CPU_TYPE_68020 assert m.get_cpu_name() == "68020" assert m.get_ram_total_kib() == 2048 assert m.max_cycles == 128 assert m.cycles_per_run == 2000 assert m.get_label_mgr()
def machine_machine_cfg_test(): cfg = ConfigDict({ 'cpu': '68020', 'ram_size': 2048, 'max_cycles': 128, 'cycles_per_run': 2000 }) m = Machine.from_cfg(cfg, True) assert m assert m.get_cpu_type() == Machine.CPU_TYPE_68020 assert m.get_cpu_name() == '68020' assert m.get_ram_total_kib() == 2048 assert m.max_cycles == 128 assert m.cycles_per_run == 2000 assert m.get_label_mgr()
def machine_disasm_block_dump_test(): mach = Machine() disasm = DisAsm(mach) buf = b"\x4e\x75" + b"\x10\x1c" + b"\x48\xe7\x3f\x3e" + b"\x48\xe7" code = disasm.disassemble_block(buf, 0x100) result = [] def store(line): result.append(line) disasm.dump_block(code, store) assert result == [ "00000100: 4e75 rts", "00000102: 101c move.b (A4)+, D0", "00000104: 48e7 3f3e movem.l D2-D7/A2-A6, -(A7)" ]
def setup(): machine = Machine() mem = machine.get_mem() alloc = MemoryAlloc.for_machine(machine) sp = machine.get_ram_begin() - 4 # setup exec exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 520 * 6) exec_lib.setup() exec_lib.fill_funcs() exec_base = exec_lib.get_addr() mem.w32(4, exec_base) machine.set_zero_mem(0, exec_base) return machine, alloc, sp, mem, exec_lib
def libnative_initres_autoinit_test(buildlibnix): machine = Machine() mem = machine.get_mem() cpu = machine.get_cpu() traps = machine.get_traps() alloc = MemoryAlloc.for_machine(machine) init_addr = machine.get_ram_begin() - 4 sp = init_addr - 4 # load lib seglist, addr, size, end = load_lib(alloc, buildlibnix) # setup init func def init_func(op, pc): assert cpu.r_reg(REG_A0) == seglist.get_baddr() trap_id = traps.setup(init_func, auto_rts=True) mem.w16(init_addr, trap_id | 0xA000) # fake vectors vectors = 0x100 mem.w32(vectors, 0x400) mem.w32(vectors + 4, 0x600) mem.w32(vectors + 8, 0x800) mem.w32(vectors + 12, 0xFFFFFFFF) # build fake resident res = Resident.alloc(alloc, "bla.library", "blub") res.setup(flags=ResidentFlags.RTF_AUTOINIT, version=42, type=NodeType.NT_LIBRARY, pri=-7) auto_init = AutoInit.alloc(alloc) auto_init.setup(functions=vectors, init_func=init_addr) res.set_auto_init(auto_init) # setup exec lib exec_lib = ExecLibrary.alloc(alloc, "exec.library", "bla", 36) exec_lib.setup() mem.w32(4, exec_lib.get_addr()) # init resident ir = InitRes(machine, alloc) lib_base, mem_obj = ir.init_resident(res.get_addr(), seglist.get_baddr(), run_sp=sp, exec_lib=exec_lib) assert lib_base assert mem_obj seglist.free() res.free() auto_init.free() alloc.free_memory(mem_obj) exec_lib.free() traps.free(trap_id) assert alloc.is_all_free()
def setup(main_profiler=None, prof_names=None, prof_calls=False): machine = Machine() alloc = MemoryAlloc(machine.get_mem(), machine.get_ram_begin()) mgr = VLibManager(machine, alloc, main_profiler=main_profiler, prof_names=prof_names, prof_calls=prof_calls) # setup ctx map cpu = machine.get_cpu() mem = machine.get_mem() cpu_type = machine.get_cpu_type() segloader = SegmentLoader(alloc) exec_ctx = ExecLibCtx(machine, alloc, segloader, None) mgr.add_ctx('exec.library', exec_ctx) mgr.add_impl_cls('exec.library', ExecLibrary) mgr.add_impl_cls('vamostest.library', VamosTestLibrary) mgr.add_impl_cls('vamostestdev.device', VamosTestDevice) return machine, alloc, mgr