def main():
result_file = r'./results/dummy.vcd'
args = parse()
ana = Analysis(input=root) # create analysis object to host prototyping project
ana.set_target(target_name='fpga') # set the active target to 'fpga'
if args.gen_bitstream:
ana.gen_sources() # generate functional models
ana.build() # generate bitstream for project
ctrl_handle = ana.launch(debug=True) # start interactive control
ctrl_handle.set_reset(1) # reset simulation
ctrl_handle.setup_trace_unit(trigger_name='time',
trigger_operator='gt',
trigger_value=1e-9,
sample_decimation=0,
) # config & arm trace unit
#ctrl_handle.set_param('emu_ctrl_data', 10000000)
#ctrl_handle.set_param('emu_ctrl_mode', 3)
ctrl_handle.set_param('emu_ctrl_mode', 1)
ctrl_handle.set_reset(0) # start simulation
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.sleep_emu(1e-6)
#sleep(0.1)
time = ctrl_handle.get_emu_time()
print(f'Paused at:{time}')
ctrl_handle.wait_on_and_dump_trace(result_file=result_file) # wait till trace buffer is full and dump to result file
ana.view(result_file=result_file) # view waveform
def main():
args = parse()
ana = Analysis(
input=root) # create analysis object to host prototyping project
ana.gen_sources() # generate functional models
ana.set_target(target_name='fpga') # set the active target to 'fpga'
if args.gen_bitstream:
ana.build() # generate bitstream for project
ctrl_handle = ana.launch(debug=True) # start interactive control
ctrl_handle.set_reset(1) # reset simulation
ctrl_handle.setup_trace_unit(trigger_name='time',
trigger_operator='gt',
trigger_value=5.5,
sample_decimation=800,
sample_count=16384) # config & arm trace unit
ctrl_handle.set_reset(0) # start simulation
ctrl_handle.wait_on_and_dump_trace(
) # wait till trace buffer is full and dump to result file
ana.view() # view waveform
def test_3():
# build bitstream
ana = Analysis(input=str(THIS_DIR))
ana.set_target(target_name='fpga')
ana.build()
def test_2():
ana = Analysis(input=root)
ana.gen_sources()
ana.set_target(target_name='fpga')
ana.build()