def cli(ctx, board, project_dir, verbose): """Clean the previous generated files.""" exit_code = SCons(project_dir).clean({ 'board': board, 'verbose': { 'all': verbose } }) ctx.exit(exit_code)
def cli(ctx, board, project_dir, verbose): """Verify the verilog code.""" exit_code = SCons(project_dir).verify({ 'board': board, 'verbose': { 'all': verbose } }) ctx.exit(exit_code)
def cli(ctx, all, top, nostyle, nowarn, warn, project_dir): """Lint the verilog code.""" exit_code = SCons(project_dir).lint({ 'all': all, 'top': top, 'nostyle': nostyle, 'nowarn': nowarn, 'warn': warn }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size): """Synthesize the bitstream.""" # Run scons exit_code = SCons().build({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size): """Bitstream timing analysis.""" # Run scons exit_code = SCons().time({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }) ctx.exit(exit_code)
def cli(ctx, device, board, fpga, pack, type, size): """Upload the bitstream to the FPGA.""" # Run scons exit_code = SCons().upload( { 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }, device) ctx.exit(exit_code)
def cli(ctx, device, board, fpga, pack, type, size, project_dir): """Upload the bitstream to the FPGA.""" drivers = Drivers() drivers.pre_upload() # Run scons exit_code = SCons(project_dir).upload( { 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }, device) drivers.post_upload() ctx.exit(exit_code)
def cli(ctx, board, serial_port, ftdi_id, sram, project_dir, verbose, verbose_yosys, verbose_nextpnr): """Upload the bitstream to the FPGA.""" drivers = Drivers() drivers.pre_upload() # Run scons exit_code = SCons(project_dir).upload( { 'board': board, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'nextpnr': verbose_nextpnr } }, serial_port, ftdi_id, sram) drivers.post_upload() ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size, project_dir, verbose, verbose_yosys, verbose_pnr): """Bitstream timing analysis.""" # Run scons exit_code = SCons(project_dir).time({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'pnr': verbose_pnr } }) ctx.exit(exit_code)
def cli(ctx, board, fpga, pack, type, size, project_dir, verbose, verbose_yosys, verbose_pnr): """Synthesize the bitstream.""" # Run scons exit_code = SCons(project_dir).build({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack, 'verbose': { 'all': verbose, 'yosys': verbose_yosys, 'pnr': verbose_pnr } }) ctx.exit(exit_code)
def __init__(self): self.board="icezum" self.scons_engine=SCons(".") #Ahora mismo da problemas self.project=Project()
class FPGA_engine(object): def __init__(self): self.board="icezum" self.scons_engine=SCons(".") #Ahora mismo da problemas self.project=Project() def config_fpga(self): print("\n\n"+pythonsays_memo+"Calling APIO FPGA Board Setup (PROJECT)"+"\n\n") #project=Project() self.project.create_ini(self.board, path, False) #apio.managers.scons.Project.create_ini(fpgaboard_name, path, False) #Another lower level option return True def verify_hdl(self): #subprocess.call('echo "\n\nCalling APIO Verify (SCONS)"' ,shell=True) print("\n\n"+pythonsays_memo+"Calling APIO Verify (SCONS)"+"\n\n") #scons_engine=SCons() self.scons_engine.verify() return True def build_hdl(self): print("\n\n"+pythonsays_memo+"BUILDING CIRCUIT"+"\n\n") #Apio building calling (SCONS) #scons_engine=SCons() ''' scons_engine.__init__()#Not needed scons_engine.build({ 'board': board, 'fpga': fpga, 'size': size, 'type': type, 'pack': pack }) ''' self.scons_engine.build({ #Details extracted from boards.json and fpgas.json Device argument must be 0 'board': "icezum", 'fpga': "iCE40-HX1K-TQ144", 'size': "1k", 'type': "hx", 'pack': "tq144" }) return True def upload_hdl(self): print("\n\n"+pythonsays_memo+"UPLOADING CIRCUIT"+"\n\n") #scons_engine=SCons() self.scons_engine.upload({ #Details extracted from boards.json and fpgas.json Device argument must be 0 'board': "icezum", 'fpga': "iCE40-HX1K-TQ144", 'size': "1k", 'type': "hx", 'pack': "tq144" }, 0) return True def verify_build_upload(self): #This functions calls apio verify and apio upload, synthesizing the circuit in the process (build) print("\n\n"+pythonsays_memo+"VERIFY_BUILD_UPLOAD"+"\n\n") if self.verify_hdl()==True: if self.upload_hdl()==True: return True
def cli(ctx): """Clean the previous generated files.""" exit_code = SCons().clean() ctx.exit(exit_code)
def __init__(self): self.board = "icezum" self.scons_engine = SCons(".") self.project = Project()
def cli(ctx, project_dir): """Clean the previous generated files.""" exit_code = SCons(project_dir).clean() ctx.exit(exit_code)
def cli(ctx, project_dir): """Launch the verilog simulation.""" exit_code = SCons(project_dir).sim() ctx.exit(exit_code)
def cli(ctx): """Verify the verilog code.""" exit_code = SCons().verify() ctx.exit(exit_code)
def cli(ctx): """Launch the verilog simulation.""" exit_code = SCons().sim() ctx.exit(exit_code)
def cli(ctx, project_dir): """Verify the verilog code.""" exit_code = SCons(project_dir).verify() ctx.exit(exit_code)