0xab: 'R_SH_GOTPLT_MEDHI16',
0xac: 'R_SH_GOTPLT_HI16',
0xb1: 'R_SH_PLT_LOW16',
0xb2: 'R_SH_PLT_MEWLOW16',
0xb3: 'R_SH_PLT_MEDHI16',
0xb4: 'R_SH_PLT_HI16',
0xb5: 'R_SH_GOTOFF_LOW16',
0xb6: 'R_SH_GOTOFF_MEWLOW16',
0xb7: 'R_SH_GOTOFF_MEDHI16',
0xb8: 'R_SH_GOTOFF_HI16',
0xb9: 'R_SH_GOTPC_LOW16',
0xba: 'R_SH_GOTPC_MEDLOW16',
0xbb: 'R_SH_GOTPC_MEDHI16',
0xbc: 'R_SH_GOTPC_HI16',
0xbd: 'R_SH_GOTPLT10BY4',
0xbf: 'R_SH_GOTPLT10BY8',
0xc1: 'R_SH_COPY64',
0xc2: 'R_SH_GLOB_DAT64',
0xc3: 'R_SH_JMP_SLOT64',
0xc4: 'R_SH_RELATIVE64',
0xfe: 'R_SH_64',
0xff: 'R_SH_64_PCREL'
}
got_section_name = '.got'
ld_linux_name = 'ld-linux-sh4.so.2'
elf_tls = TLSArchInfo(2, 56, [8], [4], [0], 0, 0)
register_arch([r'.*sh4.*|.*sh.*|em_sh', 'sh4'], 32, 'any', ArchSH4)
Register('watchlo.7', 4, 0x2748),
Register('watchhi.7', 4, 0x274c),
Register('cop0_reg20.7', 4, 0x2750),
Register('cop0_reg21.7', 4, 0x2754),
Register('cop0_reg22.7', 4, 0x2758),
Register('cop0_reg23.7', 4, 0x275c),
Register('cop0_reg24.7', 4, 0x2760),
Register('perfcnt.7', 4, 0x2764),
Register('cop0_reg26.7', 4, 0x2768),
Register('cacheerr.7', 4, 0x276c),
Register('datalo.7', 4, 0x2770),
Register('datahi.7', 4, 0x2774),
Register('cop0_reg30.7', 4, 0x2778),
Register('cop0_reg31.7', 4, 0x277c),
Register('hi', 4, 0x3000),
Register('lo', 4, 0x3004),
Register('hi1', 4, 0x3008),
Register('lo1', 4, 0x300c),
Register('hi2', 4, 0x3010),
Register('lo2', 4, 0x3014),
Register('hi3', 4, 0x3018),
Register('lo3', 4, 0x301c),
Register('tsp', 4, 0x3020),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:le:32:default'], 32, Endness.LE,
ArchPcode_MIPS_LE_32_default)
from .common import ArchPcode
class ArchPcode_HC05_BE_16_default(ArchPcode):
name = 'HC05:BE:16:default'
pcode_arch = 'HC05:BE:16:default'
description = 'HC05 (6805) Microcontroller Family'
bits = 16
ip_offset = 0x20
sp_offset = 0x22
bp_offset = sp_offset
instruction_endness = Endness.BE
register_list = [
Register('a', 1, 0x0),
Register('hix', 2, 0x10),
Register('hi', 1, 0x10),
Register('x', 1, 0x11),
Register('pc', 2, 0x20, alias_names=('ip', )),
Register('pch', 1, 0x20),
Register('pcl', 1, 0x21),
Register('sp', 2, 0x22),
Register('sph', 1, 0x22),
Register('spl', 1, 0x23),
Register('ccr', 1, 0x30)
]
register_arch(['hc05:be:16:default'], 16, Endness.BE,
ArchPcode_HC05_BE_16_default)
'r7': (14, 2),
'r8': (16, 2),
'r9': (18, 2),
'r10': (20, 2),
'r11': (22, 2),
'r12': (24, 2),
'r13': (26, 2),
'r14': (28, 2),
'r15': (30, 2)
}
argument_registers = {
registers['r4'][0],
registers['r5'][0],
registers['r6'][0],
registers['r7'][0],
registers['r8'][0],
registers['r9'][0],
registers['r10'][0],
registers['r11'][0],
registers['r12'][0],
registers['r13'][0],
registers['r14'][0],
registers['r15'][0],
}
# EDG: Can you even use PIC here? I don't think so
dynamic_tag_translation = {}
register_arch([r'msp|msp430|em_msp430'], 32, 'Iend_LE', ArchMSP430)
Register('s30', 4, 0x53dc),
Register('h30', 2, 0x53de),
Register('b30', 1, 0x53df),
Register('z31', 32, 0x53e0),
Register('q31', 16, 0x53f0),
Register('d31', 8, 0x53f8),
Register('s31', 4, 0x53fc),
Register('h31', 2, 0x53fe),
Register('b31', 1, 0x53ff),
Register('p0', 4, 0x6000),
Register('p1', 4, 0x6004),
Register('p2', 4, 0x6008),
Register('p3', 4, 0x600c),
Register('p4', 4, 0x6010),
Register('p5', 4, 0x6014),
Register('p6', 4, 0x6018),
Register('p7', 4, 0x601c),
Register('p8', 4, 0x6020),
Register('p9', 4, 0x6024),
Register('p10', 4, 0x6028),
Register('p11', 4, 0x602c),
Register('p12', 4, 0x6030),
Register('p13', 4, 0x6034),
Register('p14', 4, 0x6038),
Register('p15', 4, 0x603c)
]
register_arch(['aarch64:be:64:v8a'], 64, Endness.BE,
ArchPcode_AARCH64_BE_64_v8A)
instruction_endness = Endness.LE
register_list = [
Register('indf', 1, 0x0),
Register('tmr0', 1, 0x1),
Register('pcl', 1, 0x2),
Register('status', 1, 0x3),
Register('fsr', 1, 0x4),
Register('porta', 1, 0x5),
Register('portb', 1, 0x6),
Register('portc', 1, 0x7),
Register('portd', 1, 0x8),
Register('porte', 1, 0x9),
Register('pclath', 1, 0xa),
Register('intcon', 1, 0xb),
Register('pir1', 1, 0xc),
Register('pir2', 1, 0xd),
Register('tmr1l', 1, 0xe),
Register('tmr1h', 1, 0xf),
Register('pc', 2, 0x0, alias_names=('ip', )),
Register('stkptr', 1, 0x2),
Register('w', 1, 0x3),
Register('skipnext', 1, 0x4),
Register('irp', 1, 0x7),
Register('rp', 1, 0x8),
Register('contextreg', 4, 0x100)
]
register_arch(['pic-16:le:16:pic-16'], 16, Endness.LE,
ArchPcode_PIC_16_LE_16_PIC_16)
Register('watchlo.7', 8, 0x2790),
Register('watchhi.7', 8, 0x2798),
Register('cop0_reg20.7', 8, 0x27a0),
Register('cop0_reg21.7', 8, 0x27a8),
Register('cop0_reg22.7', 8, 0x27b0),
Register('cop0_reg23.7', 8, 0x27b8),
Register('cop0_reg24.7', 8, 0x27c0),
Register('perfcnt.7', 8, 0x27c8),
Register('cop0_reg26.7', 8, 0x27d0),
Register('cacheerr.7', 8, 0x27d8),
Register('datalo.7', 8, 0x27e0),
Register('datahi.7', 8, 0x27e8),
Register('cop0_reg30.7', 8, 0x27f0),
Register('cop0_reg31.7', 8, 0x27f8),
Register('hi', 8, 0x3000),
Register('lo', 8, 0x3008),
Register('hi1', 8, 0x3010),
Register('lo1', 8, 0x3018),
Register('hi2', 8, 0x3020),
Register('lo2', 8, 0x3028),
Register('hi3', 8, 0x3030),
Register('lo3', 8, 0x3038),
Register('tsp', 8, 0x3040),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:le:64:64-32addr'], 32, Endness.LE,
ArchPcode_MIPS_LE_64_64_32addr)
Register('watchlo.7', 8, 0x2790),
Register('watchhi.7', 8, 0x2798),
Register('cop0_reg20.7', 8, 0x27a0),
Register('cop0_reg21.7', 8, 0x27a8),
Register('cop0_reg22.7', 8, 0x27b0),
Register('cop0_reg23.7', 8, 0x27b8),
Register('cop0_reg24.7', 8, 0x27c0),
Register('perfcnt.7', 8, 0x27c8),
Register('cop0_reg26.7', 8, 0x27d0),
Register('cacheerr.7', 8, 0x27d8),
Register('datalo.7', 8, 0x27e0),
Register('datahi.7', 8, 0x27e8),
Register('cop0_reg30.7', 8, 0x27f0),
Register('cop0_reg31.7', 8, 0x27f8),
Register('hi', 8, 0x3000),
Register('lo', 8, 0x3008),
Register('hi1', 8, 0x3010),
Register('lo1', 8, 0x3018),
Register('hi2', 8, 0x3020),
Register('lo2', 8, 0x3028),
Register('hi3', 8, 0x3030),
Register('lo3', 8, 0x3038),
Register('tsp', 8, 0x3040),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:le:64:default'], 64, Endness.LE,
ArchPcode_MIPS_LE_64_default)
Register('r8l', 2, 0x1020),
Register('r8h', 2, 0x1022),
Register('r9', 4, 0x1024),
Register('r9l', 2, 0x1024),
Register('r9h', 2, 0x1026),
Register('r10', 4, 0x1028),
Register('r10l', 2, 0x1028),
Register('r10h', 2, 0x102a),
Register('r11', 4, 0x102c),
Register('r11l', 2, 0x102c),
Register('r11h', 2, 0x102e),
Register('r12', 4, 0x1030),
Register('r12l', 2, 0x1030),
Register('r12h', 2, 0x1032),
Register('sp', 4, 0x1034),
Register('spl', 2, 0x1034),
Register('sph', 2, 0x1036),
Register('lr', 4, 0x1038),
Register('lrl', 2, 0x1038),
Register('lrh', 2, 0x103a),
Register('pc', 4, 0x103c, alias_names=('ip',)),
Register('pcl', 2, 0x103c),
Register('pch', 2, 0x103e),
Register('c', 1, 0x1100),
Register('z', 1, 0x1101),
Register('n', 1, 0x1102),
Register('v', 1, 0x1103)
]
register_arch(['toy:le:32:default'], 32, Endness.LE, ArchPcode_Toy_LE_32_default)
Register('s30', 4, 0x378),
Register('s31', 4, 0x37c),
Register('q8', 16, 0x380),
Register('d16', 8, 0x380),
Register('d17', 8, 0x388),
Register('q9', 16, 0x390),
Register('d18', 8, 0x390),
Register('d19', 8, 0x398),
Register('q10', 16, 0x3a0),
Register('d20', 8, 0x3a0),
Register('d21', 8, 0x3a8),
Register('q11', 16, 0x3b0),
Register('d22', 8, 0x3b0),
Register('d23', 8, 0x3b8),
Register('q12', 16, 0x3c0),
Register('d24', 8, 0x3c0),
Register('d25', 8, 0x3c8),
Register('q13', 16, 0x3d0),
Register('d26', 8, 0x3d0),
Register('d27', 8, 0x3d8),
Register('q14', 16, 0x3e0),
Register('d28', 8, 0x3e0),
Register('d29', 8, 0x3e8),
Register('q15', 16, 0x3f0),
Register('d30', 8, 0x3f0),
Register('d31', 8, 0x3f8)
]
register_arch(['arm:le:32:v7'], 32, Endness.LE, ArchPcode_ARM_LE_32_v7)
Register('r9', 8, 0x1048),
Register('r9h', 4, 0x1048),
Register('r9l', 4, 0x104c),
Register('r10', 8, 0x1050),
Register('r10h', 4, 0x1050),
Register('r10l', 4, 0x1054),
Register('r11', 8, 0x1058),
Register('r11h', 4, 0x1058),
Register('r11l', 4, 0x105c),
Register('r12', 8, 0x1060),
Register('r12h', 4, 0x1060),
Register('r12l', 4, 0x1064),
Register('sp', 8, 0x1068),
Register('sph', 4, 0x1068),
Register('spl', 4, 0x106c),
Register('lr', 8, 0x1070),
Register('lrh', 4, 0x1070),
Register('lrl', 4, 0x1074),
Register('pc', 8, 0x1078, alias_names=('ip', )),
Register('pch', 4, 0x1078),
Register('pcl', 4, 0x107c),
Register('c', 1, 0x1100),
Register('z', 1, 0x1101),
Register('n', 1, 0x1102),
Register('v', 1, 0x1103)
]
register_arch(['toy:be:64:harvard'], 64, Endness.BE,
ArchPcode_Toy_BE_64_harvard)
general_purpose=True, vex_offset=160),
Register(name='x21', size=8, alias_names=('s5',),
general_purpose=True, vex_offset=168),
Register(name='x22', size=8, alias_names=('s6',),
general_purpose=True, vex_offset=176),
Register(name='x23', size=8, alias_names=('s7',),
general_purpose=True, vex_offset=184),
Register(name='x24', size=8, alias_names=('s8',),
general_purpose=True, vex_offset=192),
Register(name='x25', size=8, alias_names=('s9',),
general_purpose=True, vex_offset=200),
Register(name='x26', size=8, alias_names=('s10',),
general_purpose=True, vex_offset=208),
Register(name='x27', size=8, alias_names=('s11',),
general_purpose=True, vex_offset=216),
Register(name='x28', size=8, alias_names=('t3',),
general_purpose=True, vex_offset=224),
Register(name='x29', size=8, alias_names=('t4',),
general_purpose=True, vex_offset=232),
Register(name='x30', size=8, alias_names=('t5',),
general_purpose=True, vex_offset=240),
Register(name='x31', size=8, alias_names=('t6',),
general_purpose=True, vex_offset=248),
Register(name='ip', alias_names={'pc', }, size=8, vex_offset=256),
Register(name='ip_at_syscall', alias_names={}, size=8, vex_offset=264)
]
register_arch([r'riscv64|riscv|RISCV|em_riscv|em_riscv64'],
64, 'Iend_LE', ArchRISCV64)
Register('r9', 4, 0x1024),
Register('r9h', 2, 0x1024),
Register('r9l', 2, 0x1026),
Register('r10', 4, 0x1028),
Register('r10h', 2, 0x1028),
Register('r10l', 2, 0x102a),
Register('r11', 4, 0x102c),
Register('r11h', 2, 0x102c),
Register('r11l', 2, 0x102e),
Register('r12', 4, 0x1030),
Register('r12h', 2, 0x1030),
Register('r12l', 2, 0x1032),
Register('sp', 4, 0x1034),
Register('sph', 2, 0x1034),
Register('spl', 2, 0x1036),
Register('lr', 4, 0x1038),
Register('lrh', 2, 0x1038),
Register('lrl', 2, 0x103a),
Register('pc', 4, 0x103c, alias_names=('ip', )),
Register('pch', 2, 0x103c),
Register('pcl', 2, 0x103e),
Register('c', 1, 0x1100),
Register('z', 1, 0x1101),
Register('n', 1, 0x1102),
Register('v', 1, 0x1103)
]
register_arch(['toy:be:32:default'], 32, Endness.BE,
ArchPcode_Toy_BE_32_default)
Register('r8h', 2, 0x1020),
Register('r8l', 2, 0x1022),
Register('r9', 4, 0x1024),
Register('r9h', 2, 0x1024),
Register('r9l', 2, 0x1026),
Register('r10', 4, 0x1028),
Register('r10h', 2, 0x1028),
Register('r10l', 2, 0x102a),
Register('r11', 4, 0x102c),
Register('r11h', 2, 0x102c),
Register('r11l', 2, 0x102e),
Register('r12', 4, 0x1030),
Register('r12h', 2, 0x1030),
Register('r12l', 2, 0x1032),
Register('sp', 4, 0x1034),
Register('sph', 2, 0x1034),
Register('spl', 2, 0x1036),
Register('lr', 4, 0x1038),
Register('lrh', 2, 0x1038),
Register('lrl', 2, 0x103a),
Register('pc', 4, 0x103c, alias_names=('ip',)),
Register('pch', 2, 0x103c),
Register('pcl', 2, 0x103e),
Register('c', 1, 0x1100),
Register('z', 1, 0x1101),
Register('n', 1, 0x1102),
Register('v', 1, 0x1103)
]
register_arch(['toy:be:32:wordsize2'], 32, Endness.BE, ArchPcode_Toy_BE_32_wordSize2)
Register('cop0_reg17.7', 4, 0x2744),
Register('watchlo.7', 4, 0x2748),
Register('watchhi.7', 4, 0x274c),
Register('cop0_reg20.7', 4, 0x2750),
Register('cop0_reg21.7', 4, 0x2754),
Register('cop0_reg22.7', 4, 0x2758),
Register('cop0_reg23.7', 4, 0x275c),
Register('cop0_reg24.7', 4, 0x2760),
Register('perfcnt.7', 4, 0x2764),
Register('cop0_reg26.7', 4, 0x2768),
Register('cacheerr.7', 4, 0x276c),
Register('datalo.7', 4, 0x2770),
Register('datahi.7', 4, 0x2774),
Register('cop0_reg30.7', 4, 0x2778),
Register('cop0_reg31.7', 4, 0x277c),
Register('hi', 4, 0x3000),
Register('lo', 4, 0x3004),
Register('hi1', 4, 0x3008),
Register('lo1', 4, 0x300c),
Register('hi2', 4, 0x3010),
Register('lo2', 4, 0x3014),
Register('hi3', 4, 0x3018),
Register('lo3', 4, 0x301c),
Register('tsp', 4, 0x3020),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:be:32:micro'], 32, Endness.BE, ArchPcode_MIPS_BE_32_micro)
Register(name='x20', size=4, alias_names=('s4',),
general_purpose=True, vex_offset=80),
Register(name='x21', size=4, alias_names=('s5',),
general_purpose=True, vex_offset=84),
Register(name='x22', size=4, alias_names=('s6',),
general_purpose=True, vex_offset=88),
Register(name='x23', size=4, alias_names=('s7',),
general_purpose=True, vex_offset=92),
Register(name='x24', size=4, alias_names=('s8',),
general_purpose=True, vex_offset=96),
Register(name='x25', size=4, alias_names=('s9',),
general_purpose=True, vex_offset=100),
Register(name='x26', size=4, alias_names=('s10',),
general_purpose=True, vex_offset=104),
Register(name='x27', size=4, alias_names=('s11',),
general_purpose=True, vex_offset=108),
Register(name='x28', size=4, alias_names=('t3',),
general_purpose=True, vex_offset=112),
Register(name='x29', size=4, alias_names=('t4',),
general_purpose=True, vex_offset=116),
Register(name='x30', size=4, alias_names=('t5',),
general_purpose=True, vex_offset=120),
Register(name='x31', size=4, alias_names=('t6',),
general_purpose=True, vex_offset=124),
Register(name='ip', alias_names={'pc', }, size=4, vex_offset=128),
]
register_arch([r'riscv32|riscv|RISCV|em_riscv|em_riscv32'],
32, 'Iend_LE', ArchRISCV)
class ArchBF(Arch):
memory_endness = Endness.LE
bits = 64
vex_arch = None
name = "BF"
instruction_alignment = 1
# Things I did not want to include but were necessary unfortunately :-(
# self.cs_mode = capstone.CS_MODE_LITTLE_ENDIAN if endness == 'Iend_LE' else capstone.CS_MODE_BIG_ENDIAN
# END
# registers is a dictionary mapping register names, to a tuple of
# register offset, and their width, in bytes
register_list = [
Register(name="ip", size=8, vex_offset=0),
Register(name="ptr", size=8, vex_offset=8),
Register(name="inout", size=1, vex_offset=16),
Register(name="ip_at_syscall", size=8, vex_offset=24),
]
ip_offset = 0
def __init__(self, endness=Endness.LE):
# forces little endian
super().__init__(Endness.LE)
register_arch(['bf|brainfuck'], 64, 'any', ArchBF)
Register('r26', 1, 0x1a),
Register('r27', 1, 0x1b),
Register('dr28', 4, 0x1c),
Register('wr28', 2, 0x1c),
Register('r28', 1, 0x1c),
Register('r29', 1, 0x1d),
Register('wr30', 2, 0x1e),
Register('r30', 1, 0x1e),
Register('r31', 1, 0x1f),
Register('dpx', 4, 0x38),
Register('r56', 1, 0x38),
Register('dpxl', 1, 0x39),
Register('dptr', 2, 0x3a),
Register('dph', 1, 0x3a),
Register('dpl', 1, 0x3b),
Register('spx', 4, 0x3c),
Register('r60', 1, 0x3c),
Register('r61', 1, 0x3d),
Register('sph', 1, 0x3e),
Register('sp', 3, 0x40),
Register('pc', 3, 0x44, alias_names=('ip', )),
Register('psw', 1, 0x48),
Register('contextreg', 4, 0x50),
Register('jumptableguard1', 1, 0x70),
Register('jumptableguard2', 1, 0x71)
]
register_arch(['80251:be:24:default'], 16, Endness.BE,
ArchPcode_80251_BE_24_default)
Register('tablat', 1, 0xff5),
Register('tblptr', 3, 0xff6),
Register('tblptrl', 1, 0xff6),
Register('tblptrh', 1, 0xff7),
Register('tblptru', 1, 0xff8),
Register('pclat', 3, 0xff9),
Register('pcl', 1, 0xff9),
Register('pclath', 1, 0xffa),
Register('pclatu', 1, 0xffb),
Register('.stkptr', 1, 0xffc),
Register('tos', 3, 0xffd),
Register('tosl', 1, 0xffd),
Register('tosh', 1, 0xffe),
Register('tosu', 1, 0xfff),
Register('pc', 3, 0x0, alias_names=('ip', )),
Register('bad', 1, 0x3),
Register('stkptr', 1, 0x4),
Register('n', 1, 0x5),
Register('ov', 1, 0x6),
Register('z', 1, 0x7),
Register('dc', 1, 0x8),
Register('c', 1, 0x9),
Register('ws', 1, 0xa),
Register('statuss', 1, 0xb),
Register('bsrs', 1, 0xc)
]
register_arch(['pic-18:le:24:pic-18'], 24, Endness.LE,
ArchPcode_PIC_18_LE_24_PIC_18)
Register('srl_ipl1', 1, 0x609),
Register('srl_ipl0', 1, 0x60a),
Register('srl_ra', 1, 0x60b),
Register('srl_n', 1, 0x60c),
Register('srl_ov', 1, 0x60d),
Register('srl_z', 1, 0x60e),
Register('srl_c', 1, 0x60f),
Register('disi', 1, 0x610),
Register('shadow_srh_dc', 1, 0x611),
Register('shadow_srl_n', 1, 0x612),
Register('shadow_srl_ov', 1, 0x613),
Register('shadow_srl_z', 1, 0x614),
Register('shadow_srl_c', 1, 0x615),
Register('dostart_shadow', 3, 0x800),
Register('doend_shadow', 3, 0x803),
Register('wdtcount', 2, 0xa00),
Register('wdtprescalara', 2, 0xa02),
Register('wdtprescalarb', 2, 0xa04),
Register('corcon_var', 1, 0xc00),
Register('corcon_ipl3', 1, 0xc01),
Register('corcon_psv', 1, 0xc02),
Register('corcon_sfa', 1, 0xc03),
Register('dcount_shadow', 2, 0x1000),
Register('skipnextflag', 1, 0x1200),
Register('contextreg', 4, 0x1400)
]
register_arch(['pic-24e:le:24:default'], 24, Endness.LE,
ArchPcode_PIC_24E_LE_24_default)
Register('s30', 4, 0x53c0),
Register('h30', 2, 0x53c0),
Register('b30', 1, 0x53c0),
Register('z31', 32, 0x53e0),
Register('q31', 16, 0x53e0),
Register('d31', 8, 0x53e0),
Register('s31', 4, 0x53e0),
Register('h31', 2, 0x53e0),
Register('b31', 1, 0x53e0),
Register('p0', 4, 0x6000),
Register('p1', 4, 0x6004),
Register('p2', 4, 0x6008),
Register('p3', 4, 0x600c),
Register('p4', 4, 0x6010),
Register('p5', 4, 0x6014),
Register('p6', 4, 0x6018),
Register('p7', 4, 0x601c),
Register('p8', 4, 0x6020),
Register('p9', 4, 0x6024),
Register('p10', 4, 0x6028),
Register('p11', 4, 0x602c),
Register('p12', 4, 0x6030),
Register('p13', 4, 0x6034),
Register('p14', 4, 0x6038),
Register('p15', 4, 0x603c)
]
register_arch(['aarch64:le:64:v8a'], 64, Endness.LE,
ArchPcode_AARCH64_LE_64_v8A)
Register('r11', 4, 0x2c),
Register('r11_16', 2, 0x2c),
Register('r11_lo', 1, 0x2c),
Register('r11_hi', 1, 0x2d),
Register('r12', 4, 0x30),
Register('r12_16', 2, 0x30),
Register('r12_lo', 1, 0x30),
Register('r12_hi', 1, 0x31),
Register('r13', 4, 0x34),
Register('r13_16', 2, 0x34),
Register('r13_lo', 1, 0x34),
Register('r13_hi', 1, 0x35),
Register('r14', 4, 0x38),
Register('r14_16', 2, 0x38),
Register('r14_lo', 1, 0x38),
Register('r14_hi', 1, 0x39),
Register('r15', 4, 0x3c),
Register('r15_16', 2, 0x3c),
Register('r15_lo', 1, 0x3c),
Register('r15_hi', 1, 0x3d),
Register('none', 4, 0x40),
Register('none_lo', 1, 0x40),
Register('none_hi', 1, 0x41),
Register('contextreg', 4, 0x1000),
Register('cnt', 1, 0x2000)
]
register_arch(['ti_msp430x:le:32:default'], 32, Endness.LE,
ArchPcode_TI_MSP430X_LE_32_default)
Register('watchlo.7', 8, 0x2790),
Register('watchhi.7', 8, 0x2798),
Register('cop0_reg20.7', 8, 0x27a0),
Register('cop0_reg21.7', 8, 0x27a8),
Register('cop0_reg22.7', 8, 0x27b0),
Register('cop0_reg23.7', 8, 0x27b8),
Register('cop0_reg24.7', 8, 0x27c0),
Register('perfcnt.7', 8, 0x27c8),
Register('cop0_reg26.7', 8, 0x27d0),
Register('cacheerr.7', 8, 0x27d8),
Register('datalo.7', 8, 0x27e0),
Register('datahi.7', 8, 0x27e8),
Register('cop0_reg30.7', 8, 0x27f0),
Register('cop0_reg31.7', 8, 0x27f8),
Register('hi', 8, 0x3000),
Register('lo', 8, 0x3008),
Register('hi1', 8, 0x3010),
Register('lo1', 8, 0x3018),
Register('hi2', 8, 0x3020),
Register('lo2', 8, 0x3028),
Register('hi3', 8, 0x3030),
Register('lo3', 8, 0x3038),
Register('tsp', 8, 0x3040),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:be:64:64-32r6addr'], 32, Endness.BE,
ArchPcode_MIPS_BE_64_64_32R6addr)
Register('cop0_reg16.7', 4, 0x2740),
Register('cop0_reg17.7', 4, 0x2744),
Register('watchlo.7', 4, 0x2748),
Register('watchhi.7', 4, 0x274c),
Register('cop0_reg20.7', 4, 0x2750),
Register('cop0_reg21.7', 4, 0x2754),
Register('cop0_reg22.7', 4, 0x2758),
Register('cop0_reg23.7', 4, 0x275c),
Register('cop0_reg24.7', 4, 0x2760),
Register('perfcnt.7', 4, 0x2764),
Register('cop0_reg26.7', 4, 0x2768),
Register('cacheerr.7', 4, 0x276c),
Register('datalo.7', 4, 0x2770),
Register('datahi.7', 4, 0x2774),
Register('cop0_reg30.7', 4, 0x2778),
Register('cop0_reg31.7', 4, 0x277c),
Register('hi', 4, 0x3000),
Register('lo', 4, 0x3004),
Register('hi1', 4, 0x3008),
Register('lo1', 4, 0x300c),
Register('hi2', 4, 0x3010),
Register('lo2', 4, 0x3014),
Register('hi3', 4, 0x3018),
Register('lo3', 4, 0x301c),
Register('tsp', 4, 0x3020),
Register('isamodeswitch', 1, 0x3f00),
Register('contextreg', 4, 0x4000)
]
register_arch(['mips:be:32:r6'], 32, Endness.BE, ArchPcode_MIPS_BE_32_R6)
###
### This file was automatically generated
###
from archinfo.arch import register_arch, Endness, Register
from .common import ArchPcode
class ArchPcode_DATA_BE_64_default(ArchPcode):
name = 'DATA:BE:64:default'
pcode_arch = 'DATA:BE:64:default'
description = 'Raw Data File (Little Endian)'
bits = 64
ip_offset = 0x80000000
sp_offset = 0x0
bp_offset = sp_offset
instruction_endness = Endness.BE
register_list = [
Register('sp', 8, 0x0),
Register('r0', 8, 0x8),
Register('contextreg', 4, 0x100)
]
register_arch(['data:be:64:default'], 64, Endness.BE, ArchPcode_DATA_BE_64_default)
Register('xmmtmp1_da', 4, 0x1400),
Register('xmmtmp1_db', 4, 0x1404),
Register('xmmtmp1_qb', 8, 0x1408),
Register('xmmtmp1_dc', 4, 0x1408),
Register('xmmtmp1_dd', 4, 0x140c),
Register('xmmtmp2', 16, 0x1410),
Register('xmmtmp2_qa', 8, 0x1410),
Register('xmmtmp2_da', 4, 0x1410),
Register('xmmtmp2_db', 4, 0x1414),
Register('xmmtmp2_qb', 8, 0x1418),
Register('xmmtmp2_dc', 4, 0x1418),
Register('xmmtmp2_dd', 4, 0x141c),
Register('contextreg', 4, 0x2000),
Register('idtr', 6, 0x2200),
Register('idtr_limit', 2, 0x2200),
Register('idtr_address', 4, 0x2202),
Register('gdtr', 6, 0x2210),
Register('gdtr_limit', 2, 0x2210),
Register('gdtr_address', 4, 0x2212),
Register('ldtr', 6, 0x2220),
Register('ldtr_limit', 2, 0x2220),
Register('ldtr_address', 4, 0x2222),
Register('tr', 6, 0x2230),
Register('tr_limit', 2, 0x2230),
Register('tr_address', 4, 0x2232)
]
register_arch(['x86:le:32:default'], 32, Endness.LE,
ArchPcode_x86_LE_32_default)
Register('r1.l', 1, 0x103),
Register('r2', 2, 0x104),
Register('r2.h', 1, 0x104),
Register('r2.l', 1, 0x105),
Register('r3', 2, 0x106),
Register('r3.h', 1, 0x106),
Register('r3.l', 1, 0x107),
Register('r4', 2, 0x108),
Register('r4.h', 1, 0x108),
Register('r4.l', 1, 0x109),
Register('r5', 2, 0x10a),
Register('r5.h', 1, 0x10a),
Register('r5.l', 1, 0x10b),
Register('r6', 2, 0x10c),
Register('r6.h', 1, 0x10c),
Register('r6.l', 1, 0x10d),
Register('r7', 2, 0x10e),
Register('r7.h', 1, 0x10e),
Register('r7.l', 1, 0x10f),
Register('xpc', 2, 0x110),
Register('xccr', 2, 0x112),
Register('xc', 1, 0x120),
Register('xv', 1, 0x121),
Register('xz', 1, 0x122),
Register('xn', 1, 0x123)
]
register_arch(['hcs12:be:24:default'], 24, Endness.BE,
ArchPcode_HCS12_BE_24_default)
Register('r9h', 2, 0x1024),
Register('r9l', 2, 0x1026),
Register('r10', 4, 0x1028),
Register('r10h', 2, 0x1028),
Register('r10l', 2, 0x102a),
Register('r11', 4, 0x102c),
Register('r11h', 2, 0x102c),
Register('r11l', 2, 0x102e),
Register('r12', 4, 0x1030),
Register('r12h', 2, 0x1030),
Register('r12l', 2, 0x1032),
Register('sp', 4, 0x1034),
Register('sph', 2, 0x1034),
Register('spl', 2, 0x1036),
Register('lr', 4, 0x1038),
Register('lrh', 2, 0x1038),
Register('lrl', 2, 0x103a),
Register('pc', 4, 0x103c, alias_names=('ip', )),
Register('pch', 2, 0x103c),
Register('pcl', 2, 0x103e),
Register('c', 1, 0x1100),
Register('z', 1, 0x1101),
Register('n', 1, 0x1102),
Register('v', 1, 0x1103),
Register('contextreg', 8, 0x2000)
]
register_arch(['toy:be:32:builder.align2'], 32, Endness.BE,
ArchPcode_Toy_BE_32_builder_align2)
Register('s1', 4, 0x378),
Register('s0', 4, 0x37c),
Register('q7', 16, 0x380),
Register('d15', 8, 0x380),
Register('d14', 8, 0x388),
Register('q6', 16, 0x390),
Register('d13', 8, 0x390),
Register('d12', 8, 0x398),
Register('q5', 16, 0x3a0),
Register('d11', 8, 0x3a0),
Register('d10', 8, 0x3a8),
Register('q4', 16, 0x3b0),
Register('d9', 8, 0x3b0),
Register('d8', 8, 0x3b8),
Register('q3', 16, 0x3c0),
Register('d7', 8, 0x3c0),
Register('d6', 8, 0x3c8),
Register('q2', 16, 0x3d0),
Register('d5', 8, 0x3d0),
Register('d4', 8, 0x3d8),
Register('q1', 16, 0x3e0),
Register('d3', 8, 0x3e0),
Register('d2', 8, 0x3e8),
Register('q0', 16, 0x3f0),
Register('d1', 8, 0x3f0),
Register('d0', 8, 0x3f8)
]
register_arch(['arm:be:32:v8'], 32, Endness.BE, ArchPcode_ARM_BE_32_v8)
Register('tc', 4, 0x148),
Register('itt0', 4, 0x14c),
Register('itt1', 4, 0x150),
Register('dtt0', 4, 0x154),
Register('dtt1', 4, 0x158),
Register('mmusr', 4, 0x15c),
Register('urp', 4, 0x160),
Register('srp', 4, 0x164),
Register('pcr', 4, 0x168),
Register('cac', 4, 0x16c),
Register('buscr', 4, 0x180),
Register('mbb', 4, 0x184),
Register('rambar0', 4, 0x188),
Register('rambar1', 4, 0x18c),
Register('sr', 2, 0x200),
Register('acusr', 2, 0x202),
Register('glbdenom', 4, 0x300),
Register('movemptr', 4, 0x304),
Register('contextreg', 4, 0x400),
Register('fp0', 12, 0x700),
Register('fp1', 12, 0x70c),
Register('fp2', 12, 0x718),
Register('fp3', 12, 0x724),
Register('fp4', 12, 0x730),
Register('fp5', 12, 0x73c),
Register('fp6', 12, 0x748),
Register('fp7', 12, 0x754)
]
register_arch(['68000:be:32:mc68020'], 32, Endness.BE, ArchPcode_68000_BE_32_MC68020)
