def test_stm_user_registers_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11101001110000010100000000100100
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StmUserRegistersA1)
assert opcode.increment
assert opcode.word_higher
assert opcode.n == 1
assert opcode.registers == 0b0100000000100100
arm.registers.cpsr.m = 0b10000
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(2, 0x11223344)
arm.registers.set(5, 0x55667788)
arm.registers.set_lr(0xAABBCCDD)
arm.registers.cpsr.m = 0b10011
arm.emulate_cycle()
assert ram_memory[
4, 12] == b'\x44\x33\x22\x11\x88\x77\x66\x55\xDD\xCC\xBB\xAA'
def test_rfe_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101000000100001100000000000000
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory[0, 8] = b'\xDD\xcc\xbb\xaa\xf2\x33\x22\x11'
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == RfeT1
assert not opcode.increment
assert not opcode.word_higher
assert opcode.wback == 0
assert opcode.n == 0
arm.registers.set(0, 0x0F000008)
arm.emulate_cycle()
assert arm.registers.pc_store_value() == 0xAABBCCDC
assert arm.registers.cpsr.value == 0x110233f2
def test_stm_t2(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101000101000010100000000100100
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StmT2)
assert opcode.wback
assert opcode.n == 1
assert opcode.registers == 0b0100000000100100
arm.registers.set(opcode.n, 0x0F000004)
arm.registers.set(2, struct.unpack('>I', b'YREV')[0])
arm.registers.set(5, struct.unpack('>I', b'ECIN')[0])
arm.registers.set_lr(0xAABBCCDD)
arm.emulate_cycle()
assert ram_memory[4, 12] == b'VERYNICE\xDD\xCC\xBB\xAA'
assert arm.registers.get(opcode.n) == 0x0F000010
def test_ldrbt_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11111000000100000001111000000100
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 4, b'\x44\x33\x22\x11')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdrbtT1)
assert opcode.instruction == arm.opcode
assert not opcode.register_form
assert opcode.add
assert not opcode.post_index
assert opcode.t == 1
assert opcode.n == 0
assert opcode.imm32 == 4
arm.registers.set(opcode.n, 0x0F000000)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0x44
def test_ldrexd_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101000110100100001001101111111
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0, 8, b'\xaa\xbb\xcc\xdd\x11\x22\x33\x44')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == LdrexdT1
assert opcode.n == 2
assert opcode.t == 1
assert opcode.t2 == 3
arm.registers.set(opcode.n, 0x0F000000)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0xDDCCBBAA
assert arm.registers.get(opcode.t2) == 0x44332211
def test_ldrsh_register_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b0101111000001010
arm.opcode_len = 16
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 4, b'\x30\x91IN')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == LdrshRegisterT1
assert opcode.m == 0
assert opcode.n == 1
assert opcode.t == 2
assert opcode.shift_n == 0
assert opcode.shift_t == SRType.LSL
assert opcode.add
assert opcode.index
assert not opcode.wback
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.m, 4)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0xffff9130
def test_ldrd_register_a1(arm_v6_without_fetch, instruction, index, mem_offset):
arm = arm_v6_without_fetch
arm.opcode = instruction
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(mem_offset, 8, b'\x44\x33\x22\x11\x88\x77\x66\x55')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdrdRegisterA1)
assert opcode.wback
assert opcode.n == 1
assert opcode.index == index
assert opcode.add
assert opcode.m == 0
assert opcode.t == 2
assert opcode.t2 == 3
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.m, 4)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0x11223344
assert arm.registers.get(opcode.t2) == 0x55667788
assert arm.registers.get(opcode.n) == 0x0F000004
def test_strd_immediate_t1(thumb_v6_without_fetch, instruction, index, mem_offset):
arm = thumb_v6_without_fetch
arm.opcode = instruction
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == StrdImmediateT1
assert opcode.wback
assert opcode.n == 0
assert opcode.index == index
assert opcode.add
assert opcode.imm32 == 4
assert opcode.t == 1
assert opcode.t2 == 2
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.t, 0x11223344)
arm.registers.set(opcode.t2, 0x55667788)
arm.emulate_cycle()
assert ram_memory[mem_offset, 8] == b'\x44\x33\x22\x11\x88\x77\x66\x55'
assert arm.registers.get(opcode.n) == 0x0F000004
def test_strd_immediate_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
instr = 0b11100001110011010000000011110000 # Store double to SP
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
arm.opcode = instr
opcode = arm.decode_instruction(instr)
opcode = opcode.from_bitarray(instr, arm)
assert isinstance(opcode, StrdImmediateA1)
assert not opcode.wback
assert opcode.n == 13
assert opcode.index
assert opcode.add
assert opcode.imm32 == 0
assert opcode.t == 0
assert opcode.t2 == 1
arm.registers.set(opcode.n, 0x0F000004)
arm.registers.set(opcode.t, 0x11223344)
arm.registers.set(opcode.t2, 0x55667788)
arm.emulate_cycle()
assert ram_memory[4, 8] == b'\x44\x33\x22\x11\x88\x77\x66\x55'
def test_strbt_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11111000000000000001111000000000
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StrbtT1)
assert opcode.m == 0
assert opcode.imm32 == 0
assert opcode.n == 0
assert opcode.t == 1
assert opcode.shift_n == 0
assert opcode.shift_t == SRType.LSL
assert opcode.add
assert not opcode.register_form
assert not opcode.post_index
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.t, 0x11223344)
arm.emulate_cycle()
assert ram_memory[0, 4] == b'\x44\x00\x00\x00'
def test_strexb_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101000110000100001000001000000
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == StrexbT1
assert opcode.d == 0
assert opcode.n == 2
assert opcode.t == 1
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.t, 0xAABBCCDD)
arm.emulate_cycle()
assert arm.registers.get(opcode.d) == 1
assert ram_memory[4, 4] == b'\x00\x00\x00\x00'
def test_tbb_tbh_t1(thumb_v6_without_fetch, instruction, is_tbh, pc):
arm = thumb_v6_without_fetch
arm.opcode = instruction
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0, 4, b'\x10\x20\x30\x40')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == TbbTbhT1
assert opcode.is_tbh == is_tbh
assert opcode.instruction == arm.opcode
assert opcode.n == 0
assert opcode.m == 1
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.m, 1)
arm.emulate_cycle()
assert arm.registers.pc_store_value() == pc
def test_ldm_alignment_fault():
arm = ArmV6()
arm.take_reset()
instr = 0b1100100100100110
arm.opcode_len = 16
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
arm.registers.sctlr.u = 1
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(instr)
opcode = opcode.from_bitarray(instr, arm)
assert type(opcode) == LdmThumbT1
assert opcode.wback is False
assert opcode.n == 1
assert opcode.registers == 0b0000000000100110
arm.registers.set(opcode.n, 0x0F000003)
with pytest.raises(DataAbortException) as dabort_exception:
arm.execute_instruction(opcode)
assert dabort_exception.value.is_alignment_fault()
assert not dabort_exception.value.second_stage_abort()
arm.registers.take_data_abort_exception(dabort_exception.value)
assert arm.registers.get_pc() == 0x00000014
def test_ldmdb_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101001001100001000000000000010
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 8, b'\xAA\xBB\xCC\xDD\x55\x44\x33\x22')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdmdbT1)
assert opcode.wback
assert opcode.n == 0
assert opcode.registers == 0b1000000000000010
arm.registers.set(opcode.n, 0x0F00000C)
arm.emulate_cycle()
assert arm.registers.get(1) == 0xDDCCBBAA
assert arm.registers.get(0) == 0x0F000004
assert arm.registers.pc_store_value() == 0x22334454
def test_ldr_immediate_thumb_t2(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b1001100000000001
arm.opcode_len = 16
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 4, b'ECIN')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == LdrImmediateThumbT2
assert opcode.imm32 == 4
assert opcode.n == 13
assert opcode.t == 0
assert opcode.add
assert not opcode.wback
assert opcode.index
arm.registers.set(opcode.n, 0x0F000000)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == struct.unpack('>I', b'NICE')[0]
def test_ldm_user_registers_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11101001110100000100000000000010
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 8, b'\xAA\xBB\xCC\xDD\x54\x44\x33\x22')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdmUserRegistersA1)
assert opcode.increment
assert opcode.word_higher
assert opcode.n == 0
assert opcode.registers == 0b100000000000010
arm.registers.set(opcode.n, 0x0F000000)
arm.emulate_cycle()
assert arm.registers.get(1) == 0xDDCCBBAA
arm.registers.cpsr.m = 0b10000
assert arm.registers.get_lr() == 0x22334454
def test_str_immediate_arm_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11100101000000000001000000000100
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StrImmediateArmA1)
assert opcode.imm32 == 4
assert opcode.n == 0
assert opcode.t == 1
assert not opcode.add
assert opcode.index
assert not opcode.wback
arm.registers.set(opcode.n, 0x0F000008)
arm.registers.set(opcode.t, 0x11223344)
arm.emulate_cycle()
assert ram_memory[4, 4] == b'\x44\x33\x22\x11'
def test_stc2_a2(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11111100100000000000000100000001
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00100 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StcStc2A2)
assert opcode.cp == 1
assert opcode.n == 0
assert opcode.add
assert opcode.imm32 == 4
assert not opcode.index
assert not opcode.wback
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.branch_to(0xFF000000)
arm.emulate_cycle()
assert arm.registers.pc_store_value() == 0x00000004
def test_strb_immediate_thumb_t3(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11111000000000010010110000000100
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StrbImmediateThumbT3)
assert opcode.imm32 == 4
assert opcode.n == 1
assert opcode.t == 2
assert not opcode.add
assert opcode.index
assert not opcode.wback
arm.registers.set(opcode.n, 0x0F000008)
arm.registers.set(opcode.t, struct.unpack('>I', b'ECIN')[0])
arm.emulate_cycle()
assert ram_memory[4, 4] == b'N\x00\x00\x00'
def test_stmdb_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101001001000010100000000100100
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, StmdbT1)
assert opcode.wback
assert opcode.n == 1
assert opcode.registers == 0b0100000000100100
arm.registers.set(opcode.n, 0x0F000010)
arm.registers.set(2, 0x44332211)
arm.registers.set(5, 0x88776655)
arm.registers.set_lr(0xAABBCCDD)
arm.emulate_cycle()
assert ram_memory[
4, 12] == b'\x11\x22\x33\x44\x55\x66\x77\x88\xDD\xCC\xBB\xAA'
assert arm.registers.get(opcode.n) == 0x0F000004
def test_ldmdb_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11101000001100000100000000100100
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 0xc,
b'\x44\x33\x22\x11\x88\x77\x66\x55\xDD\xCC\xBB\xAA')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdmdaA1)
assert opcode.wback
assert opcode.n == 0
assert opcode.registers == 0b0100000000100100
arm.registers.set(opcode.n, 0x0F00000C)
arm.emulate_cycle()
assert arm.registers.get(2) == 0x11223344
assert arm.registers.get(5) == 0x55667788
assert arm.registers.get_lr() == 0xAABBCCDD
assert arm.registers.get(opcode.n) == 0x0F000000
def test_srs_thumb_t1(thumb_v6_without_fetch):
arm = thumb_v6_without_fetch
arm.opcode = 0b11101000000011011100000000010010
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00010 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert type(opcode) == SrsThumbT1
assert not opcode.increment
assert not opcode.word_higher
assert opcode.wback == 0
assert opcode.mode == 0b10010
arm.registers.cpsr.m = 0b10011
arm.registers.set_rmode(13, opcode.mode, 0x0F000008)
arm.registers.set_lr(0xAABBCCDD)
arm.registers.spsr_svc = 0x11223344
arm.emulate_cycle()
assert ram_memory[0, 8] == b'\xdd\xcc\xbb\xaa\x44\x33\x22\x11'
def test_ldr_register_arm_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11100111100100010010000000000000
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0x4, 4, b'\x11\x22\x33\x44')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdrRegisterArmA1)
assert opcode.m == 0
assert opcode.n == 1
assert opcode.t == 2
assert opcode.shift_n == 0
assert opcode.shift_t == SRType.LSL
assert opcode.add
assert not opcode.wback
assert opcode.index
arm.registers.set(opcode.n, 0x0F000000)
arm.registers.set(opcode.m, 4)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0x44332211
def call_function_without_stack(proc, function_binary, register_params):
function_memory = RAM(len(function_binary))
function_memory.write(0, len(function_binary), function_binary)
mc = MemoryController(function_memory, FUNCTION_BASE, FUNCTION_BASE + len(function_binary))
proc.mem.memories.append(mc)
for register_index in register_params:
proc.registers.set(register_index, register_params[register_index])
curr_pc = 0xF0000000
proc.registers.branch_to(curr_pc)
while proc.registers.pc_store_value() != 0:
proc.emulate_cycle()
def test_set():
value = 0x00000012
address_descriptor = AddressDescriptor()
address_descriptor.paddress.physicaladdress = 0x0F000000
ram_memory = RAM(0x100)
ram_memory[0, 4] = b'\x00\x00\x00\x00'
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
mch = MemoryControllerHub()
mch.memories.append(mc)
mch[address_descriptor, 4] = value
assert ram_memory[0, 4] == b'\x12\x00\x00\x00'
assert value == 0x00000012
def prepare_emulator():
arm = ArmV6()
arm.registers.sctlr.m = 0
# Add eloop in the IRQ vector
arm.mem.memories[0].mem.write(0x18, len(ELOOP), ELOOP)
# Add eloop in the desired addr
mem = RAM(len(ELOOP))
mem.write(0, len(ELOOP), ELOOP)
mc = MemoryController(mem, ADDR, ADDR + len(ELOOP))
arm.mem.memories.append(mc)
# Reboot with new settings
arm.take_reset()
# Jump to the eloop
arm.registers.branch_to(ADDR)
return arm
def strncat(destination, source, num):
arm = ArmV6()
arm.take_reset()
arm.registers.sctlr.m = 0
strings = RAM((len(destination) + len(source)) * 2)
strings[0, len(destination)] = destination
source_offset = len(destination) + len(source)
strings[source_offset, len(source)] = source
strings_base = 0xE0000000
mc = MemoryController(strings, strings_base, strings_base + strings.size)
arm.mem.memories.append(mc)
call_function_without_stack(arm, STRNCAT_IMPL, {
0: strings_base, # Address of destination string
1: strings_base + source_offset, # Address of destination string
2: num, # Address of destination string
})
return strings.read(0, min(len(destination) + len(source) - 1, num))
def test_increment_pc():
arm = ArmV6()
arm.take_reset()
prev_pc = 0x0F000000
arm.registers.sctlr.m = 0
arm.registers.branch_to(prev_pc)
ram_memory = RAM(0x100)
ram_memory[0, 2] = b'\x41\x1c'
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
arm.registers.set(0, 0x00000012)
arm.emulate_cycle()
assert not arm.registers.cpsr.n
assert not arm.registers.cpsr.z
assert not arm.registers.cpsr.c
assert not arm.registers.cpsr.v
assert arm.registers.pc_store_value() - prev_pc == 2
assert arm.registers.get(1) == 0x00000013
def test_ldrexh_a1(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11100001111100000010111110011111
arm.opcode_len = 32
# setting Data Region registers
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b00011 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
ram_memory.write(0, 4, b'\xaa\xbb\xcc\xdd')
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, LdrexhA1)
assert opcode.n == 0
assert opcode.t == 2
arm.registers.set(opcode.n, 0x0F000000)
arm.emulate_cycle()
assert arm.registers.get(opcode.t) == 0xBBAA
def test_push_a2(arm_v6_without_fetch):
arm = arm_v6_without_fetch
arm.opcode = 0b11100101001011010000000000000100
arm.opcode_len = 32
arm.registers.drsrs[0].en = 1 # enabling memory region
arm.registers.drsrs[0].rsize = 0b01000 # setting region size
arm.registers.drbars[0] = 0x0F000000 # setting region base address
arm.registers.dracrs[0].ap = 0b011 # setting access permissions
arm.registers.mpuir.iregion = 0x01 # declaring the region
arm.registers.mpuir.dregion = 0x01 # declaring the region
ram_memory = RAM(0x100)
mc = MemoryController(ram_memory, 0x0F000000, 0x0F000100)
arm.mem.memories.append(mc)
opcode = arm.decode_instruction(arm.opcode)
opcode = opcode.from_bitarray(arm.opcode, arm)
assert isinstance(opcode, PushA2)
assert opcode.registers == 0b0000000000000001
assert opcode.unaligned_allowed
arm.registers.set(0, 0x11223344)
arm.registers.set_sp(0x0F000004)
arm.emulate_cycle()
assert ram_memory[0, 4] == b'\x44\x33\x22\x11'
assert arm.registers.get_sp() == 0x0F000000
