def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
print('unpredictable')
else:
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c) if self.register_form else self.imm32
offset_addr = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = processor.registers.get(self.n) if self.post_index else offset_addr
if self.t == 15:
data = processor.registers.pc_store_value()
else:
data = processor.registers.get(self.t)
if (processor.unaligned_support() or
substring(address, 1, 0) == 0b00 or
processor.registers.current_instr_set() == InstrSet.ARM):
processor.mem_u_unpriv_set(address, 4, data)
else:
processor.mem_u_unpriv_set(address, 4, 0x00000000) # unknown
if self.post_index:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
print "unpredictable"
else:
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(
self.m), self.shift_t, self.shift_n,
processor.registers.cpsr.get_c()
) if self.register_form else self.imm32
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = processor.registers.get(
self.n) if self.post_index else offset_addr
data = processor.mem_u_unpriv_get(address, 4)
if self.post_index:
processor.registers.set(self.n, offset_addr)
if processor.unaligned_support(
) or address[30:32] == "0b00":
processor.registers.set(self.t, data)
else:
if processor.registers.current_instr_set(
) == InstrSet.InstrSet_ARM:
processor.registers.set(
self.t, ror(data, 8 * address[30:32].uint))
else:
processor.registers.set(
self.t, BitArray(length=32)) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
if self.t == 15:
data = processor.registers.pc_store_value()
else:
data = processor.registers.get(self.t)
if (processor.unaligned_support()
or lower_chunk(address, 2) == 0b00
or processor.registers.current_instr_set()
== InstrSet.ARM):
processor.mem_u_set(address, 4, data)
else:
processor.mem_u_set(address, 4, 0x00000000) # unknown
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
shifted = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(processor.registers.get(self.n), shifted, 0)
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
if processor.condition_passed():
operand = shift(processor.registers.get(self.n), 32, self.shift_t,
self.shift_n, processor.registers.cpsr.c)
result, sat = signed_sat_q(to_signed(operand, 32),
self.saturate_to)
processor.registers.set(self.d, to_unsigned(result, 32))
if sat:
processor.registers.cpsr.q = 1
def execute(self, processor):
shift_n = processor.registers.get(self.s)[24:32].uint
shifted = shift(processor.registers.get(self.m), self.shift_t, shift_n,
processor.registers.cpsr.get_c())
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), ~shifted, "1")
processor.registers.cpsr.set_n(result[0])
processor.registers.cpsr.set_z(not result.any(True))
processor.registers.cpsr.set_c(carry)
processor.registers.cpsr.set_v(overflow)
def execute(self, processor):
if processor.condition_passed():
shifted = shift(processor.registers.get(self.m), self.shift_t,
self.shift_n, processor.registers.cpsr.get_c())
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), shifted, "0")
processor.registers.cpsr.set_n(result[0])
processor.registers.cpsr.set_z(not result.any(True))
processor.registers.cpsr.set_c(carry)
processor.registers.cpsr.set_v(overflow)
def execute(self, processor):
shift_n = lower_chunk(processor.registers.get(self.s), 8)
shifted = shift(processor.registers.get(self.m), 32, self.shift_t,
shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), bit_not(shifted, 32), 1)
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
if processor.condition_passed():
operand2 = shift(processor.registers.get(self.m), self.shift_t,
self.shift_n, processor.registers.cpsr.get_c())
temp_rd = processor.registers.get(
self.n)[0:16] if self.tb_form else operand2[0:16]
temp_rd += operand2[
16:32] if self.tb_form else processor.registers.get(
self.n)[16:32]
processor.registers.set(self.d, temp_rd)
def execute(self, processor):
if processor.condition_passed():
offset = shift(processor.registers.get(self.m), self.shift_t, self.shift_n,
processor.registers.cpsr.get_c())
address = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
if self.is_pldw:
processor.hint_preload_data_for_write(address)
else:
processor.hint_preload_data(address)
def execute(self, processor):
if processor.condition_passed():
operand2 = shift(processor.registers.get(self.m), 32, self.shift_t,
self.shift_n, processor.registers.cpsr.c)
rd_15 = substring(
operand2 if self.tb_form else processor.registers.get(self.n),
15, 0)
rd_31 = substring(
processor.registers.get(self.n) if self.tb_form else operand2,
31, 16)
processor.registers.set(self.d, chain(rd_31, rd_15, 16))
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
raise UndefinedInstructionException()
elif processor.registers.current_mode_is_user_or_system():
print('unpredictable')
else:
operand2 = shift(processor.registers.get(
self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c
) if self.register_form else self.imm32
if self.opcode == 0b0000:
result = processor.registers.get(self.n) & operand2
elif self.opcode == 0b0001:
result = processor.registers.get(self.n) ^ operand2
elif self.opcode == 0b0010:
result = add_with_carry(processor.registers.get(self.n),
bit_not(operand2, 32), 1)[0]
elif self.opcode == 0b0011:
result = add_with_carry(
bit_not(processor.registers.get(self.n), 32), operand2,
1)[0]
elif self.opcode == 0b0100:
result = add_with_carry(processor.registers.get(self.n),
operand2, 0)[0]
elif self.opcode == 0b0101:
result = add_with_carry(processor.registers.get(self.n),
operand2,
processor.registers.cpsr.c)[0]
elif self.opcode == 0b0110:
result = add_with_carry(processor.registers.get(self.n),
bit_not(operand2, 32),
processor.registers.cpsr.c)[0]
elif self.opcode == 0b0111:
result = add_with_carry(
bit_not(processor.registers.get(self.n), 32), operand2,
processor.registers.cpsr.c)[0]
elif self.opcode == 0b1100:
result = processor.registers.get(self.n) | operand2
elif self.opcode == 0b1101:
result = operand2
elif self.opcode == 0b1110:
result = processor.registers.get(self.n) & bit_not(
operand2, 32)
elif self.opcode == 0b1111:
result = bit_not(operand2, 32)
processor.registers.cpsr_write_by_instr(
processor.registers.get_spsr(), 0b1111, True)
if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t:
print('unpredictable')
else:
processor.branch_write_pc(result)
def execute(self, processor):
if processor.condition_passed():
shifted = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(processor.registers.get(self.n), shifted, 0)
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(self.n)
processor.mem_u_set(address, 1, lower_chunk(processor.registers.get(self.t), 8))
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
shifted = shift(processor.registers.get(self.m), self.shift_t,
self.shift_n, processor.registers.cpsr.get_c())
result, carry, overflow = add_with_carry(
processor.registers.get_sp(), shifted, "0")
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.set_n(result[0])
processor.registers.cpsr.set_z(not result.any(True))
processor.registers.cpsr.set_c(carry)
processor.registers.cpsr.set_v(overflow)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
print "unpredictable"
else:
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), self.shift_t, self.shift_n,
processor.registers.cpsr.get_c()) if self.register_form else self.imm32
offset_addr = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = processor.registers.get(self.n) if self.post_index else offset_addr
processor.registers.set(self.t, zero_extend(processor.mem_u_unpriv_get(address, 1), 32))
if self.post_index:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32, self.shift_t,
self.shift_n, processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
data = processor.mem_u_get(address, 2)
if self.wback:
processor.registers.set(self.n, offset_addr)
if processor.unaligned_support() or not bit_at(address, 0):
processor.registers.set(self.t, sign_extend(data, 16, 32))
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), self.shift_t, self.shift_n,
processor.registers.cpsr.get_c())
offset_addr = add(processor.registers.get(self.n), offset, 32)
address = offset_addr
data = processor.mem_u_get(address, 4)
if self.t == 15:
if address[30:32] == "0b00":
processor.load_write_pc(address)
else:
print "unpredictable"
elif processor.unaligned_support() or address[30:32] == "0b00":
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t, BitArray(length=32)) # unknown
def execute(self, processor):
if processor.condition_passed():
offset = shift(processor.registers.get(self.m), 32, self.shift_t,
self.shift_n, processor.registers.cpsr.c)
n = processor.registers.get(self.n)
offset_addr = (n + offset) if self.add else (n - offset)
address = offset_addr if self.index else n
data = processor.mem_u_get(address, 4)
if self.wback:
processor.registers.set(self.n, offset_addr)
if self.t == 15:
if substring(address, 1, 0) == 0b00:
processor.load_write_pc(address)
else:
print('unpredictable')
elif processor.unaligned_support() or substring(address, 1,
0) == 0b00:
processor.registers.set(self.t, data)
else:
processor.registers.set(
self.t, ror(data, 32, 8 * substring(address, 1, 0)))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), self.shift_t,
self.shift_n, processor.registers.cpsr.get_c())
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
data = processor.mem_u_get(address, 2)
if self.wback:
processor.registers.set(self.n, offset_addr)
if processor.unaligned_support() or not address[31]:
processor.registers.set(self.t, zero_extend(data, 32))
else:
processor.registers.set(self.t,
BitArray(length=32)) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
address = add(processor.registers.get(self.n), offset, 32)
data = processor.mem_u_get(address, 4)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(address)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
offset = shift(processor.registers.get(self.m), self.shift_t,
self.shift_n, processor.registers.cpsr.get_c())
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
data = processor.mem_u_get(address, 4)
if self.wback:
processor.registers.set(self.n, offset_addr)
if self.t == 15:
if address[30:32] == "0b00":
processor.load_write_pc(address)
else:
print "unpredictable"
elif processor.unaligned_support() or address[30:32] == "0b00":
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t,
ror(data, 8 * address[30:32].uint))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
if processor.unaligned_support() or not bit_at(address, 0):
processor.mem_u_set(
address, 2,
lower_chunk(processor.registers.get(self.t), 16))
else:
processor.mem_u_set(address, 2, 0x0000) # unknown
if self.wback:
processor.registers.set(self.n, offset_addr)
