def _add_register_interface(self):
"""! @brief Add a register interface to this module group.
This method defines and adds the necessary signals to this module group
comrising an ASTERICS slave register interface.
This method is called by methods adding port-register connections."""
# Slave register interface:
# Create ports for the slave register interface
ctrl_reg = Port(
"slv_ctrl_reg",
data_type="slv_reg_data",
data_width=Port.DataWidth(0, "to", 0),
)
status_reg = Port(
"slv_status_reg",
direction="out",
data_type="slv_reg_data",
data_width=Port.DataWidth(0, "to", 0),
)
mod_reg = Port(
"slv_reg_modify",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(0, "to", 0),
)
config_reg = Port(
"slv_reg_config",
direction="out",
data_type="slv_reg_config_table",
data_width=Port.DataWidth(0, "to", 0),
)
config_const = Constant(
"slave_register_configuration",
data_type="slv_reg_config_table",
data_width=Port.DataWidth(0, "to", 0),
value="()",
)
self.entity_ports = [config_reg, ctrl_reg, status_reg, mod_reg]
self.entity_constants = [config_const]
self.constants = [config_const]
self.__assign_interfaces__()
reginter = self.get_slave_register_interface()
self.register_if = reginter
self.regmod = self.define_signal("reg_modify_vect", "std_logic_vector")
# Hack to suppress neutral value assignment; Assigned object is not used
config_reg.incoming = config_const
status_reg.incoming = config_const
mod_reg.connect(self.regmod)
def remove_port_connection(source: Port, sink: Port):
"""! @brief Remove/Undo a connection between two Ports."""
source.outgoing.remove(sink)
sink.incoming = None
source.glue_signal = None
sink.glue_signal = None
sink.set_connected(False)
def _build_layer(self):
config_dict = self.module_config_dicts[self.filter_module_entity]
# Add and configure filter modules:
for idx in range(self.filter_module_count):
modulename = self.name + "_module_" + str(idx)
filter_module = self.add_module(self.filter_module_entity,
modulename)
# Configure the filter module
for param, value in config_dict.items():
filter_module.set_generic_value(param, value)
# Select values for this filter module
if self.operation in self.OPERATIONS_REQUIREING_VALUES:
lower_bound = idx * self.filters_per_module
upper_bound = (idx + 1) * self.filters_per_module
weights = self.weight_values[lower_bound * self.
weights_per_filter:upper_bound *
self.weights_per_filter]
biases = self.bias_values[lower_bound:upper_bound]
quant_mults = self.quant_mult_values[lower_bound:upper_bound]
filter_module.assign_trained_values(weights, biases,
quant_mults)
self.filter_modules.append(filter_module)
total_output_width = self.output_bit_width * self.filter_count
data_out_inter = Interface(AsStream.INTERFACE_TYPE_NAME,
AsStream(),
default_name="out")
data_out_inter.direction = "out"
data_out_port = Port(
"data",
"results_data_out",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(total_output_width - 1, "downto", 0),
)
strobe_out_port = Port("strobe", "results_strobe_out", direction="out")
stall_out_port = Port("stall", "results_stall_out")
data_out_inter.add_port(data_out_port)
data_out_inter.add_port(strobe_out_port)
data_out_inter.add_port(stall_out_port)
strobe_signal_value = "pipeline_strobe_out_combined and {}".format(
self.outgoing_strobes_valid_signal.code_name)
strobe_out_inter_sig = self.define_signal(
"results_strobe_out_int", fixed_value=strobe_signal_value)
strobe_out_port.set_glue_signal(strobe_out_inter_sig)
strobe_out_port.incoming = strobe_out_inter_sig
strobe_out_inter_sig.outgoing.append(strobe_out_port)
stall_out_sig = self.define_signal("results_stall_out_int")
stall_out_port.outgoing.append(stall_out_sig)
stall_out_sig.incoming.append(stall_out_port)
self.pipe_manager.get_port("output_stall_in").connect(stall_out_sig)
self.flush_in_stall = stall_out_sig
self.result_interface = data_out_inter
self.result_interface.assign_to(self)
self.add_interface(self.result_interface)
