def GTECH_NOR8(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Unot(
Or(Or(Or(p['A'], p['B']), Or(p['C'], p['D'])),
Or(Or(p['E'], p['F']), Or(p['G'], p['H']))))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_ADD_AB(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval1 = Xor(p['A'], p['B'])
rval2 = And(p['A'], p['B'])
return Assign(Lvalue(LConcat([p['S'], p['COUT']])),
Rvalue(Concat([rval1, rval2])))
def SELECT_OP(instance):
p = __get_instance_ports(instance)
control_count = int((len(p) - 1) / 2)
cond_stmt = IntConst('1\'b0')
for i in range(control_count, 0, -1):
cond_stmt = Cond(p['CONTROL%d' % i], p['DATA%d' % i], cond_stmt)
return Assign(Lvalue(p['Z']), Rvalue(cond_stmt))
def GTECH_MUX8(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Cond(
p['C'],
Cond(p['B'], Cond(p['A'], p['D7'], p['D6']),
Cond(p['A'], p['D5'], p['D4'])),
Cond(p['B'], Cond(p['A'], p['D3'], p['D2']),
Cond(p['A'], p['D1'], p['D0'])))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def MUX_OP(instance):
p = __get_instance_ports(instance)
for c in range(32):
if len(p) == 1 + c + 2**c:
break
cond_stmt = IntConst('1\'b0')
for i in range(control_count, 0, -1):
cond_stmt = Cond(p['CONTROL%d' % i], p['DATA%d' % i], cond_stmt)
return Assign(Lvalue(p['Z']), Rvalue(cond_stmt))
def GTECH_OA21(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = And(Or(p['A'], p['B']), p['C'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_OR_NOT(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Or(p['A'], Unot(p['B']))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_XNOR4(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Unot(Xor(Xor(p['A'], p['B']), Xor(p['C'], p['D'])))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def DIV_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = Divide(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def ASHR_TC_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = Sra(SystemCall('signed', [p['A']]), p['SH'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_MUXI2(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Unot(Cond(p['S'], p['B'], p['A']))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def LEQ_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = LessEq(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GT_TC_OP(instance):
p = __get_instance_ports(instance)
rval = GreaterThan(SystemCall('signed', [p['A']]),
SystemCall('signed', [p['B']]))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GT_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = GreaterThan(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def MULT_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = Times(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def SUB_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = Minus(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_AOI2N2(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Unot(Or(And(p['A'], p['B']), Unot(Or(p['C'], p['D']))))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def LEQ_TC_OP(instance):
p = __get_instance_ports(instance)
rval = LessEq(SystemCall('signed', [p['A']]),
SystemCall('signed', [p['B']]))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_MAJ23(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Or(Or(And(p['A'], p['B']), And(p['A'], p['C'])),
And(p['B'], p['C']))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_TBUF(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Cond(p['E'], p['A'], IntConst('1\'bz'))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_NOT(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
return Assign(Lvalue(p['Z']), Rvalue(Unot(p['A'])))
def GTECH_NAND3(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Unot(And(And(p['A'], p['B']), p['C']))
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_XOR2(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = Xor(p['A'], p['B'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def ASHR_UNS_UNS_OP(instance):
p = __get_instance_ports(instance)
rval = Srl(p['A'], p['SH'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_AND5(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
rval = And(And(And(p['A'], p['B']), And(p['C'], p['D'])), p['E'])
return Assign(Lvalue(p['Z']), Rvalue(rval))
def GTECH_ONE(instance):
p = __get_instance_ports(instance)
if 'Z' not in p: return None
return Assign(Lvalue(p['Z']), Rvalue(IntConst('1\'b1')))
def SEQGEN(instance, wires, regs):
p = __get_instance_ports(instance)
# Get configuration booleans
has_clock = (p['clocked_on'] != IntConst('1\'b0'))
has_async_reset = (p['clear'] != IntConst('1\'b0'))
has_async_set = (p['preset'] != IntConst('1\'b0'))
has_async_enable = (p['enable'] != IntConst('1\'b0'))
has_async_data = (p['data_in'] != IntConst('1\'b0'))
has_sync_reset = (p['synch_clear'] != IntConst('1\'b0'))
has_sync_set = (p['synch_preset'] != IntConst('1\'b0'))
has_sync_enable = (p['synch_enable'] != IntConst('1\'b0'))
has_sync_data = (p['next_state'] != IntConst('1\'b0'))
has_sync_toggle = (p['synch_toggle'] != IntConst('1\'b0'))
has_noninverted_output = ('Q' in p)
has_inverted_output = ('QN' in p)
# Log configuration
logging.debug('SEQGEN Configuration:')
logging.debug(
('\t %s: ' + ('\t' * 3) + '%s') % ('has_clock', str(has_clock)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_async_reset', str(has_async_reset)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_async_set', str(has_async_set)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_async_enable', str(has_async_enable)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_async_data', str(has_async_data)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_sync_reset', str(has_sync_reset)))
logging.debug(
('\t %s: ' + ('\t' * 3) + '%s') % ('has_sync_set', str(has_sync_set)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_sync_enable', str(has_sync_enable)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_sync_data', str(has_sync_data)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_sync_toggle', str(has_sync_toggle)))
logging.debug(('\t %s: ' + ('\t' * 1) + '%s') %
('has_noninverted_output', str(has_noninverted_output)))
logging.debug(('\t %s: ' + ('\t' * 2) + '%s') %
('has_inverted_output', str(has_inverted_output)))
# Assert all assumptions before moving on to early catch unexpected configurations
assert not (has_async_reset and has_sync_reset)
assert not (has_async_set and has_sync_set)
assert not (has_async_enable and has_sync_enable)
assert not (has_async_data and has_sync_data)
assert not (has_clock and has_async_data)
assert (has_noninverted_output or has_inverted_output)
# Not sure what to do with the synchronous toggle pin (couldn't find the RTL
# that synthesizes this configuration pin, could be rare / unused?)
if has_sync_toggle:
logging.error('No implementation defined for %s replacement!' %
sys._getframe().f_code.co_name)
return InstanceList(instance.module, [], [instance])
# EN pin
if has_sync_enable: EN = p['synch_enable']
elif has_async_enable: EN = p['enable']
else: EN = None
# RESET pin
if has_sync_reset: RESET = p['synch_clear']
elif has_async_reset: RESET = p['clear']
else: RESET = None
# SET pin
if has_sync_set: SET = p['synch_preset']
elif has_async_set: SET = p['preset']
else: SET = None
# DATA pin
DATA = p['data_in'] if has_async_data else p['next_state']
# OUTPUT pins
Q = p['Q'] if has_noninverted_output else None
QN = p['QN'] if has_inverted_output else None
# Main data assign block
assigns = []
if Q: assigns.append(NonblockingSubstitution(Lvalue(Q), Rvalue(DATA)))
if QN:
assigns.append(NonblockingSubstitution(Lvalue(QN), Rvalue(Unot(DATA))))
stmt = Block(assigns)
# Add enable if it exists
if EN:
stmt = IfStatement(EN, stmt, None)
# Add set if it exists
if SET:
assigns = []
if Q:
assigns.append(
NonblockingSubstitution(Lvalue(Q), Rvalue(IntConst('1\'b1'))))
if QN:
assigns.append(
NonblockingSubstitution(Lvalue(QN), Rvalue(IntConst('1\'b0'))))
stmt = IfStatement(SET, Block(assigns), stmt)
# Add reset if it exists
if RESET:
assigns = []
if Q:
assigns.append(
NonblockingSubstitution(Lvalue(Q), Rvalue(IntConst('1\'b0'))))
if QN:
assigns.append(
NonblockingSubstitution(Lvalue(QN), Rvalue(IntConst('1\'b1'))))
stmt = IfStatement(RESET, Block(assigns), stmt)
# Create the sensitivity list
sens = []
if has_clock: sens.append(Sens(p['clocked_on'], type='posedge'))
if has_async_data: sens.append(Sens(p['data_in'], type='level'))
if has_async_enable: sens.append(Sens(p['enable'], type='level'))
if has_async_reset: sens.append(Sens(p['clear'], type='level'))
if has_async_set: sens.append(Sens(p['preset'], type='level'))
# Convert the outputs from wires to regs
if has_noninverted_output: __convert_pin_to_reg(p['Q'], wires, regs)
if has_inverted_output: __convert_pin_to_reg(p['QN'], wires, regs)
# Return always block AST
return Always(SensList(sens),
stmt if type(stmt) == Block else Block([stmt]))
def TSGEN( instance, wires, regs, assigns ):
p = __get_instance_ports(instance)
rval = Cond(p['three_state'], IntConst('1\'bz'), p['function'])
return Assign(Lvalue(p['output']), Rvalue(rval))
