def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
srcop = self.src_operand
immop = self.imm_operand
srcval = simstate.rhs(iaddr, srcop)
immval = immop.opkind.to_unsigned_int()
expr = str(srcval) + ' >> ' + str(immval)
result: SV.SimValue = SV.simUndefinedDW
if srcval.is_undefined:
simstate.add_logmsg("warning",
"srl: operand is undefined: " + str(srcop))
elif srcval.is_literal:
srcval = SV.mk_simvalue(srcval.literal_value)
result = (SV.mk_simvalue(srcval.literal_value)).bitwise_srl(immval)
elif srcval.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif srcval.is_address:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
else:
simstate.add_logmsg("warning",
"srl: operand not recognized: " + str(srcval))
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + ' < ' + str(src2val)
if src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg("warning",
"slt: some operand is undefined: " + expr)
elif src1val.is_literal and src2val.is_literal:
v1 = SV.mk_simvalue(src1val.literal_value)
v2 = SV.mk_simvalue(src2val.literal_value)
if v1.to_signed_int() < v2.to_signed_int():
result = SV.simOne
else:
result = SV.simZero
else:
result = SV.simUndefinedDW
simstate.add_logmsg("warning",
"slt: some operand is not recognized: " + expr)
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
srcop = self.src_operand
immop = self.imm_operand
dstop = self.dst_operand
srcval = simstate.rhs(iaddr, srcop)
immval = immop.opkind.value
expr = str(srcval) + " < " + str(immval)
if srcval.is_undefined:
result = SV.simUndefinedDW
simstate.add_logmsg("warning",
"slti: operand not defined: " + str(srcop))
elif srcval.is_literal:
v = SV.mk_simvalue(srcval.literal_value)
if v.to_signed_int() < immval:
result = SV.simOne
else:
result = SV.simZero
elif srcval.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
else:
result = SV.simUndefinedDW
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + " xor " + str(src2val)
if src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif src1val.is_literal and src2val.is_literal:
v1 = SV.mk_simvalue(src1val.literal_value)
v2 = SV.mk_simvalue(src2val.literal_value)
result = v1.bitwise_xor(v2)
else:
result = SV.simUndefinedDW
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + ' == ' + str(src2val)
if src1val.is_undefined or src2val.is_undefined:
raise SU.CHBSimError(
simstate,
iaddr,
"teq: some operands are undefined: " + expr)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, src1op, expr)
elif src1val.is_literal and src2val.is_literal:
if src1val.literal_value == src2val.literal_value:
raise SU.CHBSimTrapSignalException(
simstate, iaddr, src1val, src2val)
else:
simstate.increment_programcounter()
return 'trap if equal: ' + expr
else:
raise SU.CHBSimError(
simstate,
iaddr,
"teq: some operands not recognized: " + expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
srcop = self.src_operand
immop = self.imm_operand
dstop = self.dst_operand
srcval = simstate.rhs(iaddr, srcop)
immval = immop.opkind.to_unsigned_int()
imm = SV.SimDoubleWordValue(immval)
expr = str(srcval) + ' | ' + str(immval)
if srcval.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg(
"warning",
"ori: operand is undefined: " + str(srcop))
elif srcval.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
if srcval.is_literal:
result = SV.mk_simvalue(srcval.literal_value).bitwise_or(imm)
else:
result = SV.simUndefinedDW
simstate.add_logmsg(
"warning",
"ori: operand not recognized: " + str(srcval))
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + " * " + str(src2val)
if src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg("warning",
"mul: some operand is undefined: " + expr)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif src1val.is_literal and src2val.is_literal:
result = SV.mk_simvalue(src1val.literal_value *
src2val.literal_value)
else:
raise SU.CHBSimError(
simstate, iaddr,
"mul: some operand to mul not recognized: " + expr)
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr,
simstate,
lhs,
result,
intermediates=str(lhs) + ' := ' + expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + ' >> ' + str(src2val)
result: SV.SimValue = SV.simUndefinedDW
if src1val.is_undefined or src2val.is_undefined:
simstate.add_logmsg("warning",
"srlv: some operand is undefined: " + expr)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif src1val.is_literal and src2val.is_literal:
v1 = SV.mk_simvalue(src1val.literal_value)
result = v1.bitwise_srl(src2val.literal_value % 32)
else:
simstate.add_logmsg("warning",
"srlv: some operand not recognized: " + expr)
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
"""Subtraction with trap on overflow (trap not currently implemented)."""
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
if src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
elif src1val.is_symbol or src2val.is_symbol:
expr = str(src1val) + ' - ' + str(src2val)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif src1val.is_string_address and src2val.is_string_address:
src1val = cast(SSV.SimStringAddress, src1val)
src2val = cast(SSV.SimStringAddress, src2val)
diff = src2val.stringval.find(src1val.stringval)
result = SV.mk_simvalue(diff)
elif src1val.is_stack_address and src2val.is_stack_address:
src1val = cast(SSV.SimStackAddress, src1val)
src2val = cast(SSV.SimStackAddress, src2val)
diff = (src1val.offsetvalue - src2val.offsetvalue) % (SU.max32 + 1)
result = SV.mk_simvalue(diff)
elif src1val.is_stack_address and src2val.is_literal:
src1val = cast(SSV.SimStackAddress, src1val)
result = cast(SV.SimValue,
src1val.add_offset(-src2val.literal_value))
elif src1val.is_global_address and src2val.is_global_address:
src1val = cast(SSV.SimGlobalAddress, src1val)
src2val = cast(SSV.SimGlobalAddress, src2val)
diff = (src1val.offsetvalue - src2val.offsetvalue) % (SU.max32 + 1)
result = SV.mk_simvalue(diff)
elif src1val.is_global_address and src2val.is_literal:
src1val = cast(SSV.SimGlobalAddress, src1val)
diff = (src1val.offsetvalue - src2val.literal_value) % (SU.max32 +
1)
result = SV.mk_simvalue(diff)
elif src1val.is_literal and src2val.is_literal:
diff = (src1val.literal_value -
src2val.literal_value) % (SU.max32 + 1)
result = SV.mk_simvalue(diff)
else:
result = SV.simUndefinedDW
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result,
('val(' + str(src1op) + ') = ' + str(src1val) +
', val(' + str(src2op) + ') = ' + str(src2val)))
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
def do_assign(result: SV.SimValue) -> str:
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(
iaddr, simstate, lhs, result,
('val(' + str(src1op) + ') = ' + str(src1val) + ', val(' +
str(src2op) + ') = ' + str(src2val)))
if src1val.is_undefined or src2val.is_undefined:
return do_assign(SV.simUndefinedDW)
elif src1val.is_symbol or src2val.is_symbol:
expr = str(src1val) + ' + ' + str(src2val)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
# two global addresses, one of which is spurious
elif (src1val.is_address and src2val.is_address and src1val.is_literal
and src2val.is_literal):
if src1val.literal_value > src2val.literal_value:
src1addr = cast(SSV.SimAddress, src1val)
result = cast(SV.SimValue,
src1addr.add_offset(src2val.literal_value))
else:
src2addr = cast(SSV.SimAddress, src2val)
result = src2addr.add_offset(src1val.literal_value)
return do_assign(result)
elif src2val.is_address and src1val.is_literal:
src2addr = cast(SSV.SimAddress, src2val)
result = src2addr.add_offset(src1val.literal_value)
return do_assign(result)
elif src1val.is_address and src2val.is_literal:
src1addr = cast(SSV.SimAddress, src1val)
result = src1addr.add_offset(src2val.literal_value)
return do_assign(result)
elif src1val.is_literal and src2val.is_literal:
v1 = src1val.literal_value
v2 = src2val.literal_value
result = cast(SV.SimValue, SV.mk_simvalue(v1 + v2))
return do_assign(result)
else:
return do_assign(SV.simUndefinedDW)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
srcop = self.src_operand
immop = self.imm_operand
srcval = simstate.rhs(iaddr, srcop)
immval = immop.opkind.to_unsigned_int()
if srcval.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg(
"warning",
"sll: operand is not defined: " + str(srcop))
elif srcval.is_literal:
v = SV.mk_simvalue(srcval.literal_value)
result = v.bitwise_sll(immval)
elif srcval.is_symbol:
srcval = cast(SSV.SimSymbol, srcval)
if srcval.value is not None:
v = SV.mk_simvalue(srcval.value)
result = v.bitwise_sll(immval)
else:
raise SU.CHBSymbolicExpression(
simstate,
iaddr,
dstop,
str(srcval) + " << " + str(immval) + " (val(" + str(srcop) + "))")
else:
result = SV.simUndefinedDW
simstate.add_logmsg(
"warning",
"sll: operand not recognized: " + str(srcval))
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(
iaddr,
simstate,
lhs,
result,
"(val(" + str(srcop) + ") = " + str(srcval) + ")")
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + " < " + str(src2val)
if src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg("warning",
"sltu: operand is not defined: " + expr)
elif src1val.is_literal and src2val.is_literal:
if src1val.literal_value < src2val.literal_value:
result = SV.simOne
else:
result = SV.simZero
elif src1val.is_address and src2val.is_address:
src1addr = cast(SSV.SimAddress, src1val)
src2addr = cast(SSV.SimAddress, src2val)
if src1addr.base == src2addr.base:
if src1addr.offsetvalue < src2addr.offsetvalue:
result = SV.simOne
else:
result = SV.simZero
else:
raise SU.CHBSimError(
simstate, iaddr,
"Illegal address comparison with different bases: " +
src1addr.base + " and " + src2addr.base)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
else:
result = SV.simUndefinedDW
simstate.add_logmsg("warning",
"sltu: some operand not recognized: " + expr)
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result, expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstlo = self.dstlo_operand
dsthi = self.dsthi_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
expr = str(src1val) + " * " + str(src2val)
if src1val.is_undefined or src2val.is_undefined:
loval = cast(SV.SimValue, SV.simUndefinedDW)
hival = cast(SV.SimValue, SV.simUndefinedDW)
simstate.add_logmsg("warning",
"mult: some operand is undefined: " + expr)
elif src1val.is_symbol or src2val.is_symbol:
raise SU.CHBSymbolicExpression(simstate, iaddr, dstlo, expr)
elif src1val.is_literal and src2val.is_literal:
v1 = SV.mk_simvalue(src1val.literal_value).to_signed_int()
v2 = SV.mk_simvalue(src2val.literal_value).to_signed_int()
p = v1 * v2
if p < 0:
p = p + SU.max64 + 1
loval = SV.mk_simvalue(p % (SU.max32 + 1))
hival = SV.mk_simvalue(p >> 32)
else:
loval = SV.simUndefinedDW
hival = SV.simUndefinedDW
simstate.add_logmsg("warning",
"mult: some operand is not a literal: " + expr)
lhslo = simstate.set(iaddr, dstlo, loval)
lhshi = simstate.set(iaddr, dsthi, hival)
simstate.increment_programcounter()
return SU.simassign(iaddr,
simstate,
lhslo,
loval,
intermediates=str(lhshi) + ' := ' + str(hival))
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dsthi = self.dsthi_operand
dstlo = self.dstlo_operand
srcrs = self.rs_operand
srcrt = self.rt_operand
src1val = simstate.rhs(iaddr, srcrs)
src2val = simstate.rhs(iaddr, srcrt)
if src1val.is_undefined or src2val.is_undefined:
resultlo = SV.simUndefinedDW
resulthi = SV.simUndefinedDW
simstate.add_logmsg(
"warning", "some operand of division not defined: " +
str(src1val) + " / " + str(src2val))
elif src1val.is_symbol or src2val.is_symbol:
expr = str(src1val) + " / " + str(src2val)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstlo, expr)
elif src1val.is_literal and src2val.is_literal:
v1 = src1val.literal_value
v2 = src2val.literal_value
resultlo = cast(SV.SimDoubleWordValue, SV.mk_simvalue(v1 // v2))
resulthi = cast(SV.SimDoubleWordValue, SV.mk_simvalue(v1 % v2))
else:
resultlo = SV.simUndefinedDW
resulthi = SV.simUndefinedDW
simstate.add_logmsg(
"warning", "some operand of division not recognized: " +
str(src1val) + " / " + str(src2val))
lhslo = simstate.set(iaddr, dstlo, resultlo)
lhshi = simstate.set(iaddr, dsthi, resulthi)
simstate.increment_programcounter()
return SU.simassign(iaddr,
simstate,
lhslo,
resultlo,
intermediates=str(lhshi) + ' := ' + str(resulthi))
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
if src1val.is_undefined or src2val.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
# address alignment
elif (src1val.is_address and src2val.is_literal
and hex(src2val.literal_value).startswith("0xffffff")):
src1val = cast(SSV.SimAddress, src1val)
result = src1val.align(src2val.literal_value)
elif (src2val.is_address and src1val.is_literal
and hex(src1val.literal_value).startswith("0xffffff")):
src2val = cast(SSV.SimAddress, src2val)
result = src2val.align(src1val.literal_value)
elif src1val.is_literal and src2val.is_literal:
v1 = SV.mk_simvalue(src1val.literal_value)
v2 = SV.mk_simvalue(src2val.literal_value)
result = v1.bitwise_and(v2)
elif src1val.is_symbol or src2val.is_symbol:
expr = str(src1val) + " =&" + str(src2val)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
else:
result = SV.simUndefinedDW
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result,
('val(' + str(src1op) + ') = ' + str(src1val) +
', val(' + str(src2op) + ') = ' + str(src2val)))
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
srcop = self.src_operand
srcval = simstate.rhs(iaddr, srcop)
immval = self.imm_operand.to_signed_int()
imm = SV.mk_simvalue(immval)
def do_assign(result: SV.SimValue) -> str:
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result,
"val(" + str(srcop) + ") = " + str(srcval))
if srcval.is_undefined:
return do_assign(SV.simUndefinedDW)
if srcval.is_symbol:
expr = str(srcval) + ' + ' + str(immval)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif srcval.is_address:
srcval = cast(SSV.SimAddress, srcval)
return do_assign(srcval.add_offset(immval))
elif srcval.is_literal:
return do_assign(SV.mk_simvalue(srcval.literal_value + immval))
elif srcval.is_string_address:
srcval = cast(SSV.SimStringAddress, srcval)
if immval == len(srcval.stringval):
result = SSV.mk_string_address('')
else:
result = SSV.mk_string_address(srcval.stringval[immval:])
return do_assign(result)
else:
return do_assign(SV.simUndefinedDW)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
dstop = self.dst_operand
srcop = self.src_operand
srcval = simstate.rhs(iaddr, srcop)
immval = SV.mk_simvalue(self.imm_operand.to_unsigned_int())
if srcval.is_undefined:
result = cast(SV.SimValue, SV.simUndefinedDW)
elif srcval.is_symbol:
expr = str(srcval) + " & " + str(immval)
raise SU.CHBSymbolicExpression(simstate, iaddr, dstop, expr)
elif srcval.is_literal:
v = SV.mk_simvalue(srcval.literal_value)
result = v.bitwise_and(immval)
else:
result = SV.simUndefinedDW
lhs = simstate.set(iaddr, dstop, result)
simstate.increment_programcounter()
return SU.simassign(iaddr, simstate, lhs, result,
'val(' + str(srcop) + ") = " + str(srcval))
