def run(self):
src_rf = self._src.get_features()
bounds = src_rf.memory_bounds
dst_rf = self._wrapper.do("get_features")
dst_number = dst_rf.memory_bounds[0]
failures = []
for number in range(bounds[0], bounds[1]):
src_mem = self._src.get_memory(number)
if src_mem.empty:
continue
try:
dst_mem = import_logic.import_mem(
self._wrapper.get_radio(),
src_rf,
src_mem,
overrides={"number": dst_number})
import_logic.import_bank(self._wrapper.get_radio(), self._src,
dst_mem, src_mem)
except import_logic.DestNotCompatible:
continue
except import_logic.ImportError, e:
failures.append(
TestFailedError("<%i>: Import Failed: %s" %
(dst_number, e)))
continue
except Exception, e:
raise TestCrashError(get_tb(), e, "[Import]")
def run(self):
src_rf = self._src.get_features()
bounds = src_rf.memory_bounds
dst_rf = self._wrapper.do("get_features")
dst_number = dst_rf.memory_bounds[0]
failures = []
for number in range(bounds[0], bounds[1]):
src_mem = self._src.get_memory(number)
if src_mem.empty:
continue
try:
dst_mem = import_logic.import_mem(self._wrapper.get_radio(),
src_rf, src_mem,
overrides={
"number": dst_number})
import_logic.import_bank(self._wrapper.get_radio(),
self._src,
dst_mem,
src_mem)
except import_logic.DestNotCompatible:
continue
except import_logic.ImportError, e:
failures.append(TestFailedError("<%i>: Import Failed: %s" %
(dst_number, e)))
continue
except Exception, e:
raise TestCrashError(get_tb(), e, "[Import]")
def test_import_bank(self):
dst_mem = chirp_common.Memory()
dst_mem.number = 1
src_mem = chirp_common.Memory()
src_mem.number = 2
dst_radio = FakeRadio(None)
src_radio = FakeRadio(None)
dst_bm = chirp_common.BankModel(dst_radio)
src_bm = chirp_common.BankModel(src_radio)
dst_banks = [
chirp_common.Bank(dst_bm, 0, 'A'),
chirp_common.Bank(dst_bm, 1, 'B'),
chirp_common.Bank(dst_bm, 2, 'C'),
]
src_banks = [
chirp_common.Bank(src_bm, 1, '1'),
chirp_common.Bank(src_bm, 2, '2'),
chirp_common.Bank(src_bm, 3, '3'),
]
self.mox.StubOutWithMock(dst_radio, 'get_mapping_models')
self.mox.StubOutWithMock(src_radio, 'get_mapping_models')
self.mox.StubOutWithMock(dst_bm, 'get_mappings')
self.mox.StubOutWithMock(src_bm, 'get_mappings')
self.mox.StubOutWithMock(dst_bm, 'get_memory_mappings')
self.mox.StubOutWithMock(src_bm, 'get_memory_mappings')
self.mox.StubOutWithMock(dst_bm, 'remove_memory_from_mapping')
self.mox.StubOutWithMock(dst_bm, 'add_memory_to_mapping')
dst_radio.get_mapping_models().AndReturn([dst_bm])
dst_bm.get_mappings().AndReturn(dst_banks)
src_radio.get_mapping_models().AndReturn([src_bm])
src_bm.get_mappings().AndReturn(src_banks)
src_bm.get_memory_mappings(src_mem).AndReturn([src_banks[0]])
dst_bm.get_memory_mappings(dst_mem).AndReturn([dst_banks[1]])
dst_bm.remove_memory_from_mapping(dst_mem, dst_banks[1])
dst_bm.add_memory_to_mapping(dst_mem, dst_banks[0])
self.mox.ReplayAll()
import_logic.import_bank(dst_radio, src_radio, dst_mem, src_mem)
def test_import_bank(self):
dst_mem = chirp_common.Memory()
dst_mem.number = 1
src_mem = chirp_common.Memory()
src_mem.number = 2
dst_radio = FakeRadio(None)
src_radio = FakeRadio(None)
dst_bm = chirp_common.BankModel(dst_radio)
src_bm = chirp_common.BankModel(src_radio)
dst_banks = [chirp_common.Bank(dst_bm, 0, 'A'),
chirp_common.Bank(dst_bm, 1, 'B'),
chirp_common.Bank(dst_bm, 2, 'C'),
]
src_banks = [chirp_common.Bank(src_bm, 1, '1'),
chirp_common.Bank(src_bm, 2, '2'),
chirp_common.Bank(src_bm, 3, '3'),
]
self.mox.StubOutWithMock(dst_radio, 'get_mapping_models')
self.mox.StubOutWithMock(src_radio, 'get_mapping_models')
self.mox.StubOutWithMock(dst_bm, 'get_mappings')
self.mox.StubOutWithMock(src_bm, 'get_mappings')
self.mox.StubOutWithMock(dst_bm, 'get_memory_mappings')
self.mox.StubOutWithMock(src_bm, 'get_memory_mappings')
self.mox.StubOutWithMock(dst_bm, 'remove_memory_from_mapping')
self.mox.StubOutWithMock(dst_bm, 'add_memory_to_mapping')
dst_radio.get_mapping_models().AndReturn([dst_bm])
dst_bm.get_mappings().AndReturn(dst_banks)
src_radio.get_mapping_models().AndReturn([src_bm])
src_bm.get_mappings().AndReturn(src_banks)
src_bm.get_memory_mappings(src_mem).AndReturn([src_banks[0]])
dst_bm.get_memory_mappings(dst_mem).AndReturn([dst_banks[1]])
dst_bm.remove_memory_from_mapping(dst_mem, dst_banks[1])
dst_bm.add_memory_to_mapping(dst_mem, dst_banks[0])
self.mox.ReplayAll()
import_logic.import_bank(dst_radio, src_radio, dst_mem, src_mem)
def execute(self, radio):
import_logic.import_bank(radio, self.__src_radio, self.__dst_mem,
self.__src_mem)
if self.cb:
gobject.idle_add(self.cb, *self.cb_args)
