def instance_builder_body(module):
constant_value = one_output.instantiate("inst1").a
# CHECK: unknown port name b
try:
inst2 = one_input.instantiate("inst2", a=constant_value)
connect(inst2.b, constant_value)
except AttributeError as e:
print(e)
# CHECK: unknown port name b
try:
inst3 = one_output.instantiate("inst3")
inst3.b
except AttributeError as e:
print(e)
# CHECK: unknown input port name nonexistant_port
try:
module.nonexistant_port
except AttributeError as e:
print(e)
# Note, the error here is actually caught and printed below.
# CHECK: Uninitialized ports remain in circuit!
# CHECK: Port: [[PORT_NAME:.+]]
# CHECK: InstanceOf: hw.module @one_input(%[[PORT_NAME]]: i32)
# CHECK: Instance: hw.instance "inst1" @one_input({{.+}})
inst1 = one_input.instantiate("inst1")
def construct(ports):
i32 = types.i32
x = hw.ConstantOp(i32, 23)
poly = PolynomialCompute(Coefficients([62, 42, 6]))("example")
connect(poly.x, x)
PolynomialCompute(coefficients=Coefficients([62, 42, 6]))("example2",
x=poly.y)
PolynomialCompute(Coefficients([1, 2, 3, 4, 5]))("example2", x=poly.y)
cp = CoolPolynomialCompute([4, 42])
cp.x.connect(23)
m = ExternWithParams(8, 3)()
m.name = "pexternInst"
ports.y = poly.y
def build(top):
dummy = hw.HWModuleOp(name='dummy',
input_ports=[('x', types.i32)],
output_ports=[('y', types.i32)],
body_builder=lambda mod: {'y': mod.x})
const = hw.ConstantOp.create(types.i32, 0)
inst = dummy.create("dummy_inst", x=const.result)
try:
# CHECK: cannot connect from source of type
connect(inst.x, None)
except TypeError as e:
print(e)
try:
# CHECK: cannot connect to destination of type
connect(None, inst.x)
except TypeError as e:
print(e)
def construct(ports):
in_ports = {
port_name: getattr(ports, port_name)
for (port_name, _) in fsm_mod._pycde_mod.input_ports
}
fsm_instance = fsm_mod(**in_ports)
# Attach clock and optional reset on the backedges created during
# the MachineOp:instatiate call.
clock_be = getattr(fsm_instance._instantiation, '_clock_backedge')
connect(clock_be, getattr(ports, clock))
if hasattr(fsm_instance._instantiation, '_reset_backedge'):
reset_be = getattr(fsm_instance._instantiation,
'_reset_backedge')
connect(reset_be, getattr(ports, reset))
# Connect outputs
for (port_name, _) in fsm_mod._pycde_mod.output_ports:
setattr(ports, port_name, getattr(fsm_instance, port_name))
def instance_builder_body(module):
# CHECK: %[[INST1_RESULT:.+]] = hw.instance "inst1" @one_output()
inst1 = one_output.create("inst1")
# CHECK: hw.instance "inst2" @one_input<BANKS: i32 = 5>(a: %[[INST1_RESULT]]: i32)
one_input.create("inst2", a=inst1.a)
# CHECK: hw.instance "inst4" @two_inputs(a: %[[INST1_RESULT]]: i32, b: %[[INST1_RESULT]]: i32)
inst4 = two_inputs.create("inst4", a=inst1.a)
connect(inst4.b, inst1.a)
# CHECK: %[[INST5_RESULT:.+]] = hw.instance "inst5" @MyWidget(my_input: %[[INST5_RESULT]]: i32)
inst5 = op.create("inst5")
connect(inst5.my_input, inst5.my_output)
# CHECK: hw.instance "inst6" @one_input<BANKS: i32 = 2>(a:
one_input.create("inst6",
a=inst1.a,
parameters={"BANKS": IntegerAttr.get(i32, 2)})
def build(mod, dummy_mod):
# CHECK: %[[C0:.+]] = hw.constant 0
const = hw.ConstantOp.create(types.i32, 0)
inst = dummy_mod.create("d")
connect(inst.x, inst.y)
connect(inst.x, const)
connect(inst.x, const.result)
def top(module):
# CHECK: %[[RESET_VAL:.+]] = hw.constant 0
reg_reset = hw.ConstantOp.create(i32, 0).result
# CHECK: %[[INPUT_VAL:.+]] = hw.constant 45
reg_input = hw.ConstantOp.create(i32, 45).result
# CHECK: %[[DATA_VAL:.+]] = seq.compreg %[[INPUT_VAL]], %clk, %rstn, %[[RESET_VAL]]
reg = seq.CompRegOp(i32,
reg_input,
module.clk,
reset=module.rstn,
reset_value=reg_reset,
name="my_reg")
# CHECK: seq.compreg %[[INPUT_VAL]], %clk
seq.reg(reg_input, module.clk)
# CHECK: seq.compreg %[[INPUT_VAL]], %clk, %rstn, %{{.+}}
seq.reg(reg_input, module.clk, reset=module.rstn)
# CHECK: %[[RESET_VALUE:.+]] = hw.constant 123
# CHECK: seq.compreg %[[INPUT_VAL]], %clk, %rstn, %[[RESET_VALUE]]
custom_reset = hw.ConstantOp.create(i32, 123).result
seq.reg(reg_input,
module.clk,
reset=module.rstn,
reset_value=custom_reset)
# CHECK: %FuBar = seq.compreg {{.+}}
seq.reg(reg_input, module.clk, name="FuBar")
# CHECK: %reg1 = seq.compreg %[[INPUT_VAL]], %clk {sv.attributes = [#sv.attribute<"no_merge">]} : i32
sv_attr = sv.SVAttributeAttr.get("no_merge")
reg1 = seq.CompRegOp.create(i32, clk=module.clk, name="reg1")
reg1.attributes["sv.attributes"] = ArrayAttr.get([sv_attr])
connect(reg1.input, reg_input)
# CHECK: %reg2 = seq.compreg %[[INPUT_VAL]], %clk
reg2 = seq.CompRegOp.create(i32, name="reg2")
connect(reg2.input, reg_input)
connect(reg2.clk, module.clk)
# CHECK: seq.compreg sym @reg1
seq.CompRegOp.create(i32,
input=reg_input,
clk=module.clk,
sym_name="reg1")
# CHECK: hw.output %[[DATA_VAL]]
hw.OutputOp([reg.data])
def connect(self, obj, result_type=None):
if result_type is None:
result_type = self.type
val = _obj_to_value(obj, self.type, result_type)
support.connect(self, val)
