def test_syn_yosys(self):
# synthesize and check equiv
s = syn(self.s27, "Yosys", print_output=False)
m = miter(self.s27, s)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
def test_bench_output(self):
g = cg.from_lib(f"b17_C")
g2 = cg.bench_to_circuit(cg.circuit_to_bench(g), g.name)
m = miter(g, g2)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
def test_fast_verilog(self):
g = cg.from_file(f"{self.test_path}/../c432.v")
gf = cg.from_file(f"{self.test_path}/../c432.v", fast=True)
self.assertSetEqual(g.inputs(), gf.inputs())
self.assertSetEqual(g.outputs(), gf.outputs())
self.assertSetEqual(g.nodes(), gf.nodes())
self.assertSetEqual(g.edges(), gf.edges())
m = miter(g, gf)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
def test_syn_genus(self):
if "CIRCUITGRAPH_GENUS_LIBRARY_PATH" in os.environ:
s = syn(self.s27, "Genus", print_output=False)
m = miter(self.s27, s)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
for f in glob.glob(f"{os.getcwd()}/genus.cmd*"):
os.remove(f)
for f in glob.glob(f"{os.getcwd()}/genus.log*"):
os.remove(f)
shutil.rmtree(f"{os.getcwd()}/fv")
def test_gtech_verilog(self):
g = cg.from_file(f"{self.test_path}/../c432.v")
with tempfile.TemporaryDirectory(
prefix="circuitgraph_test_dir") as tmpdirname:
g_syn = cg.syn(g,
engine="dc",
suppress_output=True,
working_dir=tmpdirname)
m = miter(g, g_syn)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
def test_miter(self):
# check self equivalence
m = miter(self.s27)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
# check equivalence with incorrect copy
m = miter(self.s27, self.s27m)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertTrue(different_output)
# check equivalence with free inputs
startpoints = self.s27.startpoints() - set(["clk"])
startpoints.pop()
m = miter(self.s27, startpoints=startpoints)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertTrue(different_output)
def test_verilog_output(self):
for g in [
cg.from_lib("test_correct_io", name="test_module_0"),
cg.from_lib("test_correct_io", name="test_module_1"),
cg.from_lib("test_correct_io", name="test_module_2"),
cg.from_lib("test_correct_io", name="test_module_3"),
]:
g2 = verilog_to_circuit(circuit_to_verilog(g), g.name)
m = miter(g, g2)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
if different_output:
import code
code.interact(local=dict(globals(), **locals()))
self.assertFalse(different_output)
def test_verilog_output(self):
for g in [
cg.from_file(
f"{self.test_path}/test_correct_io.v",
name="test_module_bb",
blackboxes=self.bbs,
),
cg.from_file(f"{self.test_path}/test_correct_io.v",
name="test_correct_io"),
]:
g2 = cg.verilog_to_circuit(cg.circuit_to_verilog(g),
g.name,
blackboxes=self.bbs)
m = miter(cg.strip_blackboxes(g), cg.strip_blackboxes(g2))
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)