Esempio n. 1
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 def MeasurePedestalDistribution(self,opt=1):
     cmd = cmd_lib.CMD(self)
     self.NumSoftwareEvtsPerWin = opt
     f = self.OpenEthLinkAndDataFile()
     self.SoftwareTriggeredDataCollectionLoop(cmd,f)
     self.TurnOffTrigsAndHV_ClosePortsAndFiles(cmd,f)
     self.ConvertDataToRootFile("temp/pedsTemp.root")
Esempio n. 2
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 def MeasureTrigDAC_and_HV_DAC_BaseValues(self):
     cmd = cmd_lib.CMD(self)
     for ASIC in range(10):
         if ((2**ASIC & int(self.ASICmask,2)) > 0):
             thBase   = [3200 for i in range(15)]
             HVbase   = [255  for i in range(15)]
             ETH.open()
             #self.SendCountScalersConfig(ETH)
             #ETH.send(cmd.CountScalersConfig())
             ETH.send(ETH.syncwd + 'AF4A0136'+'AE000100')
             time.sleep(0.1)
             ETH.send(cmd.Reg47_NumClkCyclesForTrigScalerCounter(self.ScalerCntNum16BitCycles))
             if (self.DEBUG): ETH.KLMprint(cmd.Reg47_NumClkCyclesForTrigScalerCounter(self.ScalerCntNum16BitCycles) ,"Number of 16bit clock cycles for scaler counting")
             time.sleep(0.1)
             for ch in range(15):
                 if ((2**ch & int(self.HVmask,2)) > 0):
                     ETH.send(cmd.HVoff())
                     time.sleep(0.1)
                     ETH.send(cmd.THoff())
                     time.sleep(0.1)
                     thBase[ch] = self.ScanForThresholdBase(cmd,ASIC,ch)
                     time.sleep(0.01)
                     HVbase[ch] = self.ScanForHVbase(cmd,ASIC,ch,thBase)
                     ETH.send(cmd.HVoff())
                     time.sleep(0.01)
                     ETH.send(cmd.THoff())
                     time.sleep(0.1)
             ETH.close()
             self.WriteHVandThBaseValuesToFile(ASIC,thBase,HVbase)
             self.PrintThList(thBase)
             self.PrintHVList(HVbase)
Esempio n. 3
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 def CollectASICtriggeredData(self):
     cmd = cmd_lib.CMD(self)
     f = self.OpenEthLinkAndDataFile()
     self.MainDataCollectionLoop(cmd,f)
     self.TurnOffTrigsAndHV_ClosePortsAndFiles(cmd,f)
     self.ConvertDataToRootFile()
     self.SaveDataCollectionParameters()
Esempio n. 4
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time.sleep(0.1)

######################################### Only need to
##         TAKE CALIB DATA             ## do this once
######################################### per raw HV setting
#for ASIC in range(10):
#    if ((2**ASIC & int(ASICmask,2)) > 0):
#        os.system("sudo ./py/ThresholdScan/SingleASIC_Starting_Values.py %s %s %d %s" % (SN,strRawHV,ASIC,HVmask))
#        time.sleep(0.1)
#time.sleep(0.1)
#print("Threshold scan finished.\n\n")
#
ctrl = linkEth.UDP(
    '192.168.20.5', '24576', '192.168.20.1', '28672',
    "eth4")  # (addr_fpga, port_fpga, addr_pc, port_pc, interface):
cmd = cmd_lib.CMD(SN, strRawHV, ASICmask)
cmdHVoff = cmd.Generate_ASIC_HV_cmd(0, [255 for i in range(15)])
cmdThOff = cmd.Generate_ASIC_TH_cmd(0, [4095 for i in range(15)])
thBase = cmd.Get_ASIC_TH_from_file(0)
HV_DAC = cmd.Get_ASIC_HV_from_file(0)

#########################################
###   Measure Pedestal Distribution   ###
#########################################
#print("\nMeasuring pedestal distributions\n")
#numPedEvtsPerWindow = 1
#time.sleep(0.1)
#os.system("echo -n > temp/data.dat") #clean file without removing (prevents ownership change to root in this script)
#f = open('temp/data.dat','ab') #a=append, b=binary
#time.sleep(0.1)
#t1 = time.time()
Esempio n. 5
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 def CreatePedestalMasterFile(self,opt=128):
     cmd = cmd_lib.CMD(self)
     self.MeasurePedestalDistribution(opt)
     ROOT.AveragePedestalTTree(self.pedfile,int(self.ASICmask,2),float(opt))
     Print("Averaged pedestal data saved in %s%s" % (OKBLUE,self.pedfile), SOFT)
     os.system("chmod g+w %s" % self.pedfile)
Esempio n. 6
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 def CollectRandomWindowData(self):
     cmd = cmd_lib.CMD(self)
     f = self.OpenEthLinkAndDataFile()
     self.RandomWindowDataCollectionLoop(cmd,f)
     self.TurnOffTrigsAndHV_ClosePortsAndFiles(cmd,f)
     self.ConvertDataToRootFile()
Esempio n. 7
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run.NumEvts = 10
run.ASICmask = "0000000001"  # e.g. 0000000111 for enabling ASICs 0, 1, and 2
run.HVmask = "0100000000000001"  #16-ch mask: 0= 255 trim DAC counts, 1= HV DAC from file
run.TrigMask = "0000000000000001"  #16-ch mask: 0= 4095 trig DAC counts, 1= trig DAC from file
run.HVDAC_offset = [-25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -25]
run.ThDAC_offset = [-425, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
run.FWpedSubType = 3  ##  1 for FW pedSub  ##  2 for peds only  ##  3 for raw data  ##
run.ParserPedSubType = "-NoPedSub"  ##  "-FWpeds"  ##  "-SWpeds"  ##  "-NoPedSub"  ##
### Uncomment block to TAKE CALIBRATION DATA
#for ASIC in range(10):
# if ((2**ASIC & int(run.ASICmask,2)) > 0):
#     os.system("./py/ThresholdScan/SingleASIC_Starting_Values.py %s %s %d %s" % (run.SN,run.strHV,ASIC,run.HVmask))
#     time.sleep(0.1)

# Construct command and linkEth classes for building and sending hex packets to FPGA
cmd = cmd_lib.CMD(run)
ctrl = linkEth.UDP(
    '192.168.20.5', '24576', '192.168.20.1', '28672',
    "eth4")  # (addr_fpga, port_fpga, addr_pc, port_pc, interface):

### Uncomment block to MEASURE PEDESTAL DISTRIBUTION
run.NumSoftwareEvtsPerWin = 128
f = run.OpenEthLinkAndDataFile(ctrl)
run.SoftwareTriggeredDataCollectionLoop(ctrl, cmd, f)
run.TurnOffTrigsAndHV_ClosePortsAndFiles(ctrl, cmd, f)
run.ConvertDataToRootFile("temp/pedsTemp.root")
run.CreatePedestalMasterFile()
#run.Plot_Peds_OneASIC()

### Uncomment block to COLLECT DATA
#f = run.OpenEthLinkAndDataFile(ctrl)