assert dut.mybits.value.binstr.lower() == "00", "The assigned value was incorrect"
dut.mybits.value = BinaryValue("ZX")
await Timer(1, "ns")
print(dut.mybits.value.binstr)
if cocotb.SIM_NAME.lower().startswith(("icarus", "ncsim", "xmsim")):
assert dut.mybits.value.binstr.lower() == "zx", "The assigned value was not as expected"
elif cocotb.SIM_NAME.lower().startswith(("riviera",)):
assert dut.mybits.value.binstr.lower() == "01", "The assigned value was not as expected"
else:
assert dut.mybits.value.binstr.lower() == "00", "The assigned value was incorrect"
@cocotb.test(
# Icarus up to (and including) 10.3 doesn't support bit-selects, see https://github.com/steveicarus/iverilog/issues/323
expect_error=IndexError if (cocotb.SIM_NAME.lower().startswith("icarus") and (IcarusVersion(cocotb.SIM_VERSION) <= IcarusVersion("10.3 (stable)"))) else (),
skip=cocotb.LANGUAGE in ["vhdl"])
async def access_single_bit(dut):
"""Access a single bit in a vector of the DUT"""
dut.stream_in_data.value = 0
await Timer(1, "ns")
dut.stream_in_data[2].value = 1
await Timer(1, "ns")
assert dut.stream_out_data_comb.value.integer == (1 << 2)
@cocotb.test()
async def access_single_bit_erroneous(dut):
"""Access a non-existent single bit"""
with pytest.raises(IndexError):
dut.stream_in_data[100000]
if cocotb.SIM_NAME.lower().startswith(("icarus", "ncsim", "xmsim")):
assert dut.mybits.value.binstr.lower(
) == "zx", "The assigned value was not as expected"
elif cocotb.SIM_NAME.lower().startswith(("riviera", )):
assert dut.mybits.value.binstr.lower(
) == "01", "The assigned value was not as expected"
else:
assert dut.mybits.value.binstr.lower(
) == "00", "The assigned value was incorrect"
@cocotb.test(
# Icarus up to (including) 10.3 doesn't support bit-selects, see https://github.com/steveicarus/iverilog/issues/323
expect_error=IndexError if
(cocotb.SIM_NAME.lower().startswith("icarus") and
(IcarusVersion(cocotb.SIM_VERSION) <= IcarusVersion("10.3 (stable)")))
else (),
skip=cocotb.LANGUAGE in ["vhdl"])
async def access_single_bit(dut):
"""Access a single bit in a vector of the DUT"""
dut.stream_in_data.value = 0
await Timer(1, "ns")
dut._log.info("%s = %d bits" %
(dut.stream_in_data._path, len(dut.stream_in_data)))
dut.stream_in_data[2].value = 1
await Timer(1, "ns")
if dut.stream_out_data_comb.value.integer != (1 << 2):
raise TestError("%s.%s != %d" %
(dut.stream_out_data_comb._path,
dut.stream_out_data_comb.value.integer, (1 << 2)))
await Timer(1, 'step')
assert dut.stream_in_data.value == pack_bit_vector(**d)
@cocotb.test()
async def test_assigning_setattr_syntax_deprecated(dut):
with assert_deprecated():
dut.stream_in_data = 1
with assert_raises(AttributeError):
# attempt to use __setattr__ syntax on signal that doesn't exist
dut.does_not_exist = 0
icarus_under_11 = cocotb.SIM_NAME.lower().startswith("icarus") and (IcarusVersion(cocotb.SIM_VERSION) <= IcarusVersion("10.3 (stable)"))
# indexing packed arrays is not supported in iverilog < 11 (gh-2586) or GHDL (gh-2587)
@cocotb.test(expect_error=IndexError if icarus_under_11 or cocotb.SIM_NAME.lower().startswith("ghdl") else ())
async def test_assigning_setitem_syntax_deprecated(dut):
with assert_deprecated():
dut.stream_in_data[0] = 1
with assert_deprecated():
with assert_raises(IndexError):
# attempt to use __setitem__ syntax on signal that doesn't exist
dut.stream_in_data[800000] = 1
@cocotb.test()
async def test_assigning_less_than_syntax_deprecated(dut):