class HitDefault(BusDriver):
_signals = ['CLK40', 'ANALOG_HIT', 'TRIGGER', 'RESETB_EXT']
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.CLK40)
self.hit = BinaryValue(bits=len(self.bus.ANALOG_HIT))
self.hit.value = 0
@cocotb.coroutine
def run(self):
self.bus.ANALOG_HIT <= self.hit
self.bus.TRIGGER <= 0
while 1:
yield RisingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESETB_EXT.value.integer
if (res == 1):
break
yield RisingEdge(self.clock)
yield Timer(100)
self.hit.assign(0x3)
self.bus.ANALOG_HIT.value = self.hit
def Ram_Read(self,dut, A):
Ad = BinaryValue()
Ad.assign(A)
#print Ad, Bd
dut.a_adbus.value = Ad
yield RisingEdge(self.dut.clk)
yield ReadOnly()
raise ReturnValue(dut.a_data_out.value)
def mask_data(self, data: BinaryValue, empty: int) -> BinaryValue:
"""Returns data signal masked according to empty signal. """
be = self.first_symbol_in_higher_order_bits
vec = BinaryValue(bigEndian=be)
val = data.value.binstr[:-empty] if be else data.value.binstr[empty:]
vec.assign(val)
if not vec.is_resolvable:
raise ci.InterfaceProtocolError(
f"Signal ({str(self['data'])} is unresolvable.")
return vec
def Ram_write(self,dut, A, B):
Ad = BinaryValue()
Ad.assign(A)
Bd = BinaryValue()
Bd.assign(B)
dut.a_adbus.value = Bd
dut.a_data_in.value = Ad
dut.a_w.value=1
yield RisingEdge(self.dut.clk)
dut.a_w.value=0
yield ReadOnly()
def Ram_Read(self,dut, A):
############# Reading value from RAM
Ad = BinaryValue()
Ad.assign(A)
#print Ad, Bd
dut.a_adbus.value = Ad
yield RisingEdge(self.dut.clk)
yield ReadOnly()
raise ReturnValue(dut.a_data_out.value)
def Ram_write(self,dut, A, B):
###### Writing value from RAM
Ad = BinaryValue()
Ad.assign(A)
Bd = BinaryValue()
Bd.assign(B)
dut.a_adbus.value = Bd
dut.a_data_in.value = Ad
dut.a_w.value=1
yield RisingEdge(self.dut.clk)
dut.a_w.value=0
yield ReadOnly()
def _driver_send(self, value, sync=True):
"""Send a transmission over the bus.
Args:
value: data to drive onto the bus.
"""
self.log.debug("Sending Avalon transmission: %r", value)
# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
word = BinaryValue(n_bits=len(self.bus.data), bigEndian=False)
# Drive some defaults since we don't know what state we're in
self.bus.valid <= 0
if sync:
yield clkedge
# Insert a gap where valid is low
if not self.on:
self.bus.valid <= 0
for _ in range(self.off):
yield clkedge
# Grab the next set of on/off values
self._next_valids()
# Consume a valid cycle
if self.on is not True and self.on:
self.on -= 1
self.bus.valid <= 1
word.assign(value)
self.bus.data <= word
# If this is a bus with a ready signal, wait for this word to
# be acknowledged
if hasattr(self.bus, "ready"):
yield self._wait_ready()
yield clkedge
self.bus.valid <= 0
word.binstr = "x" * len(self.bus.data)
self.bus.data <= word
self.log.debug("Successfully sent Avalon transmission: %r", value)
def _driver_send(self, value, sync=True):
"""Send a transmission over the bus.
Args:
value: data to drive onto the bus.
"""
self.log.debug("Sending Avalon transmission: %d" % value)
# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
word = BinaryValue(n_bits=len(self.bus.data), bigEndian=False)
# Drive some defaults since we don't know what state we're in
self.bus.valid <= 0
if sync:
yield clkedge
# Insert a gap where valid is low
if not self.on:
self.bus.valid <= 0
for i in range(self.off):
yield clkedge
# Grab the next set of on/off values
self._next_valids()
# Consume a valid cycle
if self.on is not True and self.on:
self.on -= 1
self.bus.valid <= 1
word.assign(value)
self.bus.data <= word
# If this is a bus with a ready signal, wait for this word to
# be acknowledged
if hasattr(self.bus, "ready"):
yield self._wait_ready()
yield clkedge
self.bus.valid <= 0
word.binstr = ("x"*len(self.bus.data))
self.bus.data <= word
self.log.debug("Successfully sent Avalon transmission: %d" % value)
def PUSH(self,dut, A,command):
Ad = BinaryValue()
Ad.assign(A)
dut.Data_in_Core1_Inp.value = Ad
dut.wr_en_Core1_Inp.value=1
dut.wr_en_Core1_Cmd.value =1
dut.Data_in_Core1_Cmd.value=command
yield RisingEdge(self.dut.clk)
dut.wr_en_Core1_Inp.value=0
dut.wr_en_Core1_Cmd.value =0
yield ReadOnly()
class HitFixed(BusDriver):
_signals = ['CLK_BX', 'HIT', 'RESET_TB', 'TRIG_EXT']
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.hit = BinaryValue(bits=len(self.bus.HIT))
self.hit <= 0
self.bus.TRIG_EXT <= 0
@cocotb.coroutine
def run(self):
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
res = 0
while res == 0:
# Wait for RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield FallingEdge(self.clock)
bv = BitLogic(len(self.hit))
bv[10] = 1
bv[15] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
for _ in range(14):
# Stop HIT after 10 CLK_BX
yield FallingEdge(self.clock)
bv = BitLogic(len(self.hit))
bv.setall(False)
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 1
yield FallingEdge(self.clock)
self.bus.TRIG_EXT <= 0
# for _ in range(5):
# # Delay hit
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv[20] = 1
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 0
#
# for _ in range(10):
# # Stop HIT after 10 CLK_BX
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv.setall(False)
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 1
# yield FallingEdge(self.clock)
# self.bus.TRIG_EXT <= 0
# for _ in range(5):
# # Delay hit
# yield FallingEdge(self.clock)
# #
# bv = BitLogic(len(self.hit))
# bv[20] = 1
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 0
#
# for _ in range(10):
# # Stop HIT after 10 CLK_BX
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv.setall(False)
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 1
# yield FallingEdge(self.clock)
self.bus.TRIG_EXT <= 0
def _monitor_recv(self):
"""Watch the pins and reconstruct transactions."""
# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
rdonly = ReadOnly()
pkt = ""
in_pkt = False
invalid_cyclecount = 0
channel = None
def valid():
if hasattr(self.bus, 'ready'):
return self.bus.valid.value and self.bus.ready.value
return self.bus.valid.value
while True:
yield clkedge
yield rdonly
if self.in_reset:
continue
if valid():
invalid_cyclecount = 0
if self.bus.startofpacket.value:
if pkt:
raise AvalonProtocolError(
"Duplicate start-of-packet received on %s" %
str(self.bus.startofpacket))
pkt = ""
in_pkt = True
if not in_pkt:
raise AvalonProtocolError("Data transfer outside of "
"packet")
# Handle empty and X's in empty / data
vec = BinaryValue()
if not self.bus.endofpacket.value:
vec = self.bus.data.value
else:
value = self.bus.data.value.get_binstr()
if self.config["useEmpty"] and self.bus.empty.value.integer:
empty = self.bus.empty.value.integer * self.config[
"dataBitsPerSymbol"]
if self.config["firstSymbolInHighOrderBits"]:
value = value[:-empty]
else:
value = value[empty:]
vec.assign(value)
if not vec.is_resolvable:
raise AvalonProtocolError(
"After empty masking value is still bad? "
"Had empty {:d}, got value {:s}".format(
empty, self.bus.data.value.get_binstr()))
vec.big_endian = self.config['firstSymbolInHighOrderBits']
pkt += vec.buff
if hasattr(self.bus, 'channel'):
if channel is None:
channel = self.bus.channel.value.integer
if channel > self.config["maxChannel"]:
raise AvalonProtocolError(
"Channel value (%d) is greater than maxChannel (%d)"
% (channel, self.config["maxChannel"]))
elif self.bus.channel.value.integer != channel:
raise AvalonProtocolError(
"Channel value changed during packet")
if self.bus.endofpacket.value:
self.log.info("Received a packet of %d bytes", len(pkt))
self.log.debug(hexdump(str((pkt))))
self.channel = channel
if self.report_channel:
self._recv({"data": pkt, "channel": channel})
else:
self._recv(pkt)
pkt = ""
in_pkt = False
channel = None
else:
if in_pkt:
invalid_cyclecount += 1
if self.config["invalidTimeout"]:
if invalid_cyclecount >= self.config["invalidTimeout"]:
raise AvalonProtocolError(
"In-Packet Timeout. Didn't receive any valid data for %d cycles!"
% invalid_cyclecount)
def _monitor_recv(self):
"""Watch the pins and reconstruct transactions."""
# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
rdonly = ReadOnly()
pkt = ""
in_pkt = False
invalid_cyclecount = 0
channel = None
def valid():
if hasattr(self.bus, 'ready'):
return self.bus.valid.value and self.bus.ready.value
return self.bus.valid.value
while True:
yield clkedge
yield rdonly
if self.in_reset:
continue
if valid():
invalid_cyclecount = 0
if self.bus.startofpacket.value:
if pkt and self.config['fail_immediately']:
raise AvalonProtocolError(
"Duplicate start-of-packet received on %s" % (
str(self.bus.startofpacket)))
pkt = ""
in_pkt = True
if not in_pkt and self.config['fail_immediately']:
raise AvalonProtocolError("Data transfer outside of "
"packet")
# Handle empty and X's in empty / data
vec = BinaryValue()
if not self.bus.endofpacket.value:
vec = self.bus.data.value
else:
value = self.bus.data.value.get_binstr()
if self.config["useEmpty"] and self.bus.empty.value.integer:
empty = self.bus.empty.value.integer * self.config["dataBitsPerSymbol"]
if self.config["firstSymbolInHighOrderBits"]:
value = value[:-empty]
else:
value = value[empty:]
vec.assign(value)
if not vec.is_resolvable:
raise AvalonProtocolError("After empty masking value is still bad? Had empty {:d}, got value {:s}".format(empty, self.bus.data.value.get_binstr()))
vec.big_endian = self.config['firstSymbolInHighOrderBits']
pkt += vec.buff
if hasattr(self.bus, 'channel'):
if channel is None:
channel = self.bus.channel.value.integer
if channel > self.config["maxChannel"]:
raise AvalonProtocolError("Channel value (%d) is greater than maxChannel (%d)" % (channel,self.config["maxChannel"]))
elif self.bus.channel.value.integer != channel:
raise AvalonProtocolError("Channel value changed during packet")
if self.bus.endofpacket.value:
self.log.info("Received a packet of %d bytes" % len(pkt))
self.log.debug(hexdump(str((pkt))))
self.channel = channel
self._recv(pkt)
pkt = ""
in_pkt = False
channel = None
else :
if in_pkt :
invalid_cyclecount += 1
if self.config["invalidTimeout"] :
if invalid_cyclecount >= self.config["invalidTimeout"] :
raise AvalonProtocolError(
"In-Packet Timeout. Didn't receive any valid data for %d cycles!" %
invalid_cyclecount)
class Cmd(BusDriver):
_signals = ['CLK_BX', 'HIT', 'RESET_TB', 'TRIG_EXT', 'CMD']
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.cmd = BinaryValue(bits=len(self.bus.CMD))
self.cmd <= 0
self.bus.TRIG_EXT <= 0
self.bus.CMD <= self.cmd
@cocotb.coroutine
def run(self):
self.bus.CMD <= 0
res = 0
while res == 0:
# Wait for RESET signal
yield RisingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield RisingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 240 # sync
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 0 # NOP
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 2 # read register
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# dat = BitLogic(len(self.cmd))
# dat[:] = 0b0110101001101010 # data = 0b0000100001 = 33
# self.cmd.assign(str(dat))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv.setall(False)
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 240 # sync
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 0 # NOP
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 3 # write register
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
dat = BitLogic(len(self.cmd))
dat[:] = 0b0110101001101010 # data = 0b0000100001 = 33
self.cmd.assign(str(dat))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
dat = BitLogic(len(self.cmd))
dat[:] = 0b0111000101110001 # data = 0b0000100001 = 33
self.cmd.assign(str(dat))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv.setall(False)
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
class HitFile(BusDriver):
_signals = ['CLK_BX', 'HIT', 'RESET_TB', 'TRIG_EXT']
def __init__(self, entity, filename):
self.filename = filename
logging.info('Loading file...' + filename)
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.hit = BinaryValue(bits=len(self.bus.HIT))
self.bus.TRIG_EXT <= 0
@cocotb.coroutine
def run(self):
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
res = 0
bx = 0
while res == 0:
# Wait for RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield FallingEdge(self.clock)
bv_size = len(self.bus.HIT)
bv = BitLogic(bv_size)
tot_hist = np.zeros([bv_size], dtype=np.uint8)
trigger = 0
with open(self.filename) as hit_file:
csv_reader = csv.reader(hit_file, delimiter=',')
for file_row in csv_reader:
bcid = int(file_row[0])
col = int(file_row[1])
row = int(file_row[2])
tot = int(file_row[3])
trg = int(file_row[4])
print('loading bcid=', bcid, ' mc=', col, ' row=', row, ' tot=', tot, ' trg=', trg, ' bx=', bx)
while bx < bcid:
yield RisingEdge(self.clock)
# yield Timer(1000)
for pix in np.where(tot_hist > 0)[0]:
bv[int(pix)] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= trigger
tot_hist[tot_hist > 0] -= 1
trigger = 0
bv.setall(False)
bx += 1
if bx == bcid:
if trg:
print("+++++++++++++++++++I am going to send a trigger+++++++++++++++++++++++++++++++")
trigger = 1
if col >= 0 and col < 224 and row >= 0 and row < 224:
pixn = row + col * 448
tot_hist[pixn] = tot_hist[pixn] + tot
# else:
# raise ValueError("Error")
# Enters when csv file is completly read
else:
while np.any(tot_hist > 0): # Process hits until tot_hist is empty
yield RisingEdge(self.clock)
# yield Timer(1000)
for pix in np.where(tot_hist > 0)[0]:
bv[int(pix)] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= trigger
tot_hist[tot_hist > 0] -= 1
trigger = 0
bv.setall(False)
bx += 1
yield RisingEdge(self.clock)
#yield Timer(1000)
self.bus.HIT <= 0
self.bus.TRIG_EXT <= 0
logging.info('End of self.filename')
