def _check_mam_write(self, mem_transfer):
exp_data_words = int(len(mem_transfer.data) / (mem_transfer.DW / 8))
self.log.debug("Expecting a memory access of %d words." %
exp_data_words)
wr_data = bytearray()
self.entity.write_ready <= 1
for _ in range(exp_data_words):
yield RisingEdge(self.clock)
while not self.entity.write_valid.value:
yield RisingEdge(self.clock)
wr_data_int = self.entity.write_data.value.integer
wr_data.extend(wr_data_int.to_bytes(int(mem_transfer.DW / 8),
byteorder='big'))
# check if we're back to initial state, all data has been transferred
yield RisingEdge(self.clock)
assert_signal_value(self.entity.write_valid, 0)
assert_signal_value(self.entity.req_valid, 0)
self.entity.write_ready <= 0
# check transferred data
if wr_data != mem_transfer.data:
raise TestFailure("Got invalid data.\nSent: %s\nReceived: %s" %
(mem_transfer.data.hex(), wr_data.hex()))
def _drive_mam_read(self, mem_transfer):
dw_b = int(mem_transfer.DW / 8)
numwords = int(len(mem_transfer.data) / dw_b)
for w in range(numwords):
# XXX: obey endianness of bus here. currently big endian
dword = 0
for b in range(dw_b):
dword |= mem_transfer.data[w * dw_b + b] << ((dw_b - b - 1) * 8)
self.entity.read_data <= dword
self.entity.read_valid <= 1
yield RisingEdge(self.clock)
while not self.entity.read_ready.value:
yield RisingEdge(self.clock)
def _check_mam_request(self, mem_transfer):
self.entity.req_ready <= 1
while not self.entity.req_valid.value:
yield RisingEdge(self.clock)
self.entity.req_ready <= 0
we = (mem_transfer.operation == 'write')
assert_signal_value(self.entity.req_we, we)
assert_signal_value(self.entity.req_addr, mem_transfer.addr)
assert_signal_value(self.entity.req_burst, mem_transfer.burst)
assert_signal_value(self.entity.req_sync, mem_transfer.sync)
exp_data_words = int(len(mem_transfer.data) / (mem_transfer.DW / 8))
if mem_transfer.burst:
assert_signal_value(self.entity.req_beats, exp_data_words)
def drive(self, mem_transfer):
"""
Drive the Debug Interconnect with a memory transfer and check the
results
"""
# request
mam_transfer_request = self._create_mam_transfer(mem_transfer)
req_pkgs = self._create_di_pkgs(mam_transfer_request)
for pkg in req_pkgs:
yield self.di_writer.send_packet(pkg)
# response
if mem_transfer.operation == 'read':
rcv_data = bytearray()
while len(rcv_data) < len(mem_transfer.data):
yield RisingEdge(self.clock)
pkg = yield self.di_reader.receive_packet(set_ready=True)
self.log.debug("Received memory read response " + str(pkg))
for payload_word in pkg.payload:
rcv_data.extend(payload_word.to_bytes(2, byteorder='big'))
# check received data
if rcv_data != mem_transfer.data:
raise TestFailure("Got invalid data.\nExpected: %s\nReceived: %s" %
(mem_transfer.data.hex(), rcv_data.hex()))
# for synchronous writes: check if we received a acknowledgement packet
if mem_transfer.operation == 'write' and mem_transfer.sync:
pkg = yield self.di_reader.receive_packet(set_ready=True)
exp_sync_pkg = DiPacket()
exp_sync_pkg.set_contents(self.SENDER_DI_ADDRESS,
self.MODULE_DI_ADDRESS,
DiPacket.TYPE.EVENT.value, 0, [])
if not pkg.equal_to(self.entity, exp_sync_pkg):
raise TestFailure(
"Acknowledgement packet for sync write invalid.")