def __init__(self, dut, speed=10e9):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.tx_clk, 6.4, units="ns").start())
cocotb.start_soon(Clock(dut.rx_clk, 6.4, units="ns").start())
self.mac = EthMac(
tx_clk=dut.tx_clk,
tx_rst=dut.tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "tx_axis"),
tx_ptp_time=dut.tx_ptp_time,
tx_ptp_ts=dut.tx_ptp_ts,
tx_ptp_ts_tag=dut.tx_ptp_ts_tag,
tx_ptp_ts_valid=dut.tx_ptp_ts_valid,
rx_clk=dut.rx_clk,
rx_rst=dut.rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "rx_axis"),
rx_ptp_time=dut.rx_ptp_time,
ifg=12, speed=speed
)
self.tx_ptp = PtpClockSimTime(
ts_96=dut.tx_ptp_time,
clock=dut.tx_clk
)
self.rx_ptp = PtpClockSimTime(
ts_96=dut.rx_ptp_time,
clock=dut.rx_clk
)
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst)
self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
def __init__(self, dut):
self.dut = dut
self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE"))
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = UltraScalePlusPcieDevice(
# configuration options
pcie_generation=3,
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
rc_4tlp_straddle=False,
enable_pf1=False,
enable_client_tag=True,
enable_extended_tag=True,
enable_parity=False,
enable_rx_msg_interface=False,
enable_sriov=False,
enable_extended_configuration=False,
enable_pf0_msi=True,
enable_pf1_msi=False,
# signals
# Clock and Reset Interface
user_clk=dut.clk_250mhz,
user_reset=dut.rst_250mhz,
# user_lnk_up
# sys_clk
# sys_clk_gt
# sys_reset
# phy_rdy_out
# Requester reQuest Interface
rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
# pcie_rq_tag0
# pcie_rq_tag1
# pcie_rq_tag_av
# pcie_rq_tag_vld0
# pcie_rq_tag_vld1
# Requester Completion Interface
rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
# Completer reQuest Interface
cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
# pcie_cq_np_req
# pcie_cq_np_req_count
# Completer Completion Interface
cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=dut.cfg_mgmt_addr,
cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
cfg_mgmt_write=dut.cfg_mgmt_write,
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
cfg_mgmt_read=dut.cfg_mgmt_read,
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
# cfg_mgmt_debug_access
# Configuration Status Interface
# cfg_phy_link_down
# cfg_phy_link_status
# cfg_negotiated_width
# cfg_current_speed
cfg_max_payload=dut.cfg_max_payload,
cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status
# cfg_vf_status
# cfg_function_power_state
# cfg_vf_power_state
# cfg_link_power_state
# cfg_err_cor_out
# cfg_err_nonfatal_out
# cfg_err_fatal_out
# cfg_local_error_out
# cfg_local_error_valid
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable
# cfg_tph_st_mode
# cfg_vf_tph_requester_enable
# cfg_vf_tph_st_mode
# Configuration Received Message Interface
# cfg_msg_received
# cfg_msg_received_data
# cfg_msg_received_type
# Configuration Transmit Message Interface
# cfg_msg_transmit
# cfg_msg_transmit_type
# cfg_msg_transmit_data
# cfg_msg_transmit_done
# Configuration Flow Control Interface
cfg_fc_ph=dut.cfg_fc_ph,
cfg_fc_pd=dut.cfg_fc_pd,
cfg_fc_nph=dut.cfg_fc_nph,
cfg_fc_npd=dut.cfg_fc_npd,
cfg_fc_cplh=dut.cfg_fc_cplh,
cfg_fc_cpld=dut.cfg_fc_cpld,
cfg_fc_sel=dut.cfg_fc_sel,
# Configuration Control Interface
# cfg_hot_reset_in
# cfg_hot_reset_out
# cfg_config_space_enable
# cfg_dsn
# cfg_bus_number
# cfg_ds_port_number
# cfg_ds_bus_number
# cfg_ds_device_number
# cfg_ds_function_number
# cfg_power_state_change_ack
# cfg_power_state_change_interrupt
cfg_err_cor_in=dut.status_error_cor,
cfg_err_uncor_in=dut.status_error_uncor,
# cfg_flr_in_process
# cfg_flr_done
# cfg_vf_flr_in_process
# cfg_vf_flr_func_num
# cfg_vf_flr_done
# cfg_pm_aspm_l1_entry_reject
# cfg_pm_aspm_tx_l0s_entry_disable
# cfg_req_pm_transition_l23_ready
# cfg_link_training_enable
# Configuration Interrupt Controller Interface
# cfg_interrupt_int
# cfg_interrupt_sent
# cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=dut.
cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=dut.
cfg_interrupt_msi_pending_status_data_enable,
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
# cfg_interrupt_msix_enable
# cfg_interrupt_msix_mask
# cfg_interrupt_msix_vf_enable
# cfg_interrupt_msix_vf_mask
# cfg_interrupt_msix_address
# cfg_interrupt_msix_data
# cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface
# cfg_ext_read_received
# cfg_ext_write_received
# cfg_ext_register_number
# cfg_ext_function_number
# cfg_ext_write_data
# cfg_ext_write_byte_enable
# cfg_ext_read_data
# cfg_ext_read_data_valid
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver(self.rc)
self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0,
2**self.BAR0_APERTURE,
ext=True,
prefetch=True)
# Ethernet
cocotb.fork(Clock(dut.qsfp_rx_clk, 3.102, units="ns").start())
cocotb.fork(Clock(dut.qsfp_tx_clk, 3.102, units="ns").start())
self.qsfp_mac = EthMac(
tx_clk=dut.qsfp_tx_clk,
tx_rst=dut.qsfp_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp_tx_axis"),
tx_ptp_time=dut.qsfp_tx_ptp_time,
tx_ptp_ts=dut.qsfp_tx_ptp_ts,
tx_ptp_ts_valid=dut.qsfp_tx_ptp_ts_valid,
rx_clk=dut.qsfp_rx_clk,
rx_rst=dut.qsfp_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp_rx_axis"),
rx_ptp_time=dut.qsfp_rx_ptp_time,
ifg=12,
speed=100e9)
dut.qspi_dq_i.setimmediatevalue(0)
self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"),
dut.m_axil_cms_clk,
dut.m_axil_cms_rst,
size=256 * 1024)
self.loopback_enable = False
cocotb.fork(self._run_loopback())
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
l_tile=False,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# serr_out=dut.serr_out,
# hip_enter_err_mode=dut.hip_enter_err_mode,
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(
0,
2**len(dut.core_pcie_inst.axil_ctrl_araddr),
ext=True,
prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(
2,
2**len(dut.core_pcie_inst.axil_app_ctrl_araddr),
ext=True,
prefetch=True)
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].
rx_async_fifo_inst.m_axis_tdata)
eth_clock_period = 6.4
eth_speed = 10e9
if eth_int_if_width == 64:
# 10G
eth_clock_period = 6.4
eth_speed = 10e9
elif eth_int_if_width == 128:
# 25G
eth_clock_period = 2.56
eth_speed = 25e9
elif eth_int_if_width == 512:
# 100G
eth_clock_period = 3.102
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(
Clock(port.port_rx_clk, eth_clock_period,
units="ns").start())
cocotb.start_soon(
Clock(port.port_tx_clk, eth_clock_period,
units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12,
speed=eth_speed)
self.port_mac.append(mac)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
dut.s_axis_stat_tvalid.setimmediatevalue(0)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = UltraScalePlusPcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
rc_4tlp_straddle=False,
enable_pf1=False,
enable_client_tag=True,
enable_extended_tag=True,
enable_parity=False,
enable_rx_msg_interface=False,
enable_sriov=False,
enable_extended_configuration=False,
enable_pf0_msi=True,
enable_pf1_msi=False,
# signals
# Clock and Reset Interface
user_clk=dut.clk,
user_reset=dut.rst,
# user_lnk_up
# sys_clk
# sys_clk_gt
# sys_reset
# phy_rdy_out
# Requester reQuest Interface
rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
# pcie_rq_tag0
# pcie_rq_tag1
# pcie_rq_tag_av
# pcie_rq_tag_vld0
# pcie_rq_tag_vld1
# Requester Completion Interface
rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
# Completer reQuest Interface
cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
# pcie_cq_np_req
# pcie_cq_np_req_count
# Completer Completion Interface
cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=dut.cfg_mgmt_addr,
cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
cfg_mgmt_write=dut.cfg_mgmt_write,
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
cfg_mgmt_read=dut.cfg_mgmt_read,
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
# cfg_mgmt_debug_access
# Configuration Status Interface
# cfg_phy_link_down
# cfg_phy_link_status
# cfg_negotiated_width
# cfg_current_speed
cfg_max_payload=dut.cfg_max_payload,
cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status
# cfg_vf_status
# cfg_function_power_state
# cfg_vf_power_state
# cfg_link_power_state
# cfg_err_cor_out
# cfg_err_nonfatal_out
# cfg_err_fatal_out
# cfg_local_error_out
# cfg_local_error_valid
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable
# cfg_tph_st_mode
# cfg_vf_tph_requester_enable
# cfg_vf_tph_st_mode
# Configuration Received Message Interface
# cfg_msg_received
# cfg_msg_received_data
# cfg_msg_received_type
# Configuration Transmit Message Interface
# cfg_msg_transmit
# cfg_msg_transmit_type
# cfg_msg_transmit_data
# cfg_msg_transmit_done
# Configuration Flow Control Interface
cfg_fc_ph=dut.cfg_fc_ph,
cfg_fc_pd=dut.cfg_fc_pd,
cfg_fc_nph=dut.cfg_fc_nph,
cfg_fc_npd=dut.cfg_fc_npd,
cfg_fc_cplh=dut.cfg_fc_cplh,
cfg_fc_cpld=dut.cfg_fc_cpld,
cfg_fc_sel=dut.cfg_fc_sel,
# Configuration Control Interface
# cfg_hot_reset_in
# cfg_hot_reset_out
# cfg_config_space_enable
# cfg_dsn
# cfg_bus_number
# cfg_ds_port_number
# cfg_ds_bus_number
# cfg_ds_device_number
# cfg_ds_function_number
# cfg_power_state_change_ack
# cfg_power_state_change_interrupt
cfg_err_cor_in=dut.status_error_cor,
cfg_err_uncor_in=dut.status_error_uncor,
# cfg_flr_in_process
# cfg_flr_done
# cfg_vf_flr_in_process
# cfg_vf_flr_func_num
# cfg_vf_flr_done
# cfg_pm_aspm_l1_entry_reject
# cfg_pm_aspm_tx_l0s_entry_disable
# cfg_req_pm_transition_l23_ready
# cfg_link_training_enable
# Configuration Interrupt Controller Interface
# cfg_interrupt_int
# cfg_interrupt_sent
# cfg_interrupt_pending
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=dut.
cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=dut.
cfg_interrupt_msi_pending_status_data_enable,
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
# cfg_interrupt_msix_enable
# cfg_interrupt_msix_mask
# cfg_interrupt_msix_vf_enable
# cfg_interrupt_msix_vf_mask
# cfg_interrupt_msix_address
# cfg_interrupt_msix_data
# cfg_interrupt_msix_int
# cfg_interrupt_msix_vec_pending
# cfg_interrupt_msix_vec_pending_status
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
# Configuration Extend Interface
# cfg_ext_read_received
# cfg_ext_write_received
# cfg_ext_register_number
# cfg_ext_function_number
# cfg_ext_write_data
# cfg_ext_write_byte_enable
# cfg_ext_read_data
# cfg_ext_read_data_valid
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(
0,
2**len(dut.core_pcie_inst.axil_ctrl_araddr),
ext=True,
prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(
2,
2**len(dut.core_pcie_inst.axil_app_ctrl_araddr),
ext=True,
prefetch=True)
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].
rx_async_fifo_inst.m_axis_tdata)
eth_clock_period = 6.4
eth_speed = 10e9
if eth_int_if_width == 64:
# 10G
eth_clock_period = 6.4
eth_speed = 10e9
elif eth_int_if_width == 128:
# 25G
eth_clock_period = 2.56
eth_speed = 25e9
elif eth_int_if_width == 512:
# 100G
eth_clock_period = 3.102
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(
Clock(port.port_rx_clk, eth_clock_period,
units="ns").start())
cocotb.start_soon(
Clock(port.port_tx_clk, eth_clock_period,
units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12,
speed=eth_speed)
self.port_mac.append(mac)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
dut.s_axis_stat_tvalid.setimmediatevalue(0)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 6.206, units="ns").start())
# Ethernet
cocotb.start_soon(
Clock(dut.qsfp1_mac_1_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp1_mac_1_tx_clk, 6.206, units="ns").start())
self.qsfp1_mac_1 = EthMac(
tx_clk=dut.qsfp1_mac_1_tx_clk,
tx_rst=dut.qsfp1_mac_1_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_tx_axis"),
rx_clk=dut.qsfp1_mac_1_rx_clk,
rx_rst=dut.qsfp1_mac_1_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp1_mac_2_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp1_mac_2_tx_clk, 6.206, units="ns").start())
self.qsfp1_mac_2 = EthMac(
tx_clk=dut.qsfp1_mac_2_tx_clk,
tx_rst=dut.qsfp1_mac_2_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_tx_axis"),
rx_clk=dut.qsfp1_mac_2_rx_clk,
rx_rst=dut.qsfp1_mac_2_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp1_mac_3_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp1_mac_3_tx_clk, 6.206, units="ns").start())
self.qsfp1_mac_3 = EthMac(
tx_clk=dut.qsfp1_mac_3_tx_clk,
tx_rst=dut.qsfp1_mac_3_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_tx_axis"),
rx_clk=dut.qsfp1_mac_3_rx_clk,
rx_rst=dut.qsfp1_mac_3_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp1_mac_4_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp1_mac_4_tx_clk, 6.206, units="ns").start())
self.qsfp1_mac_4 = EthMac(
tx_clk=dut.qsfp1_mac_4_tx_clk,
tx_rst=dut.qsfp1_mac_4_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_tx_axis"),
rx_clk=dut.qsfp1_mac_4_rx_clk,
rx_rst=dut.qsfp1_mac_4_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp2_mac_1_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp2_mac_1_tx_clk, 6.206, units="ns").start())
self.qsfp2_mac_1 = EthMac(
tx_clk=dut.qsfp2_mac_1_tx_clk,
tx_rst=dut.qsfp2_mac_1_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_tx_axis"),
rx_clk=dut.qsfp2_mac_1_rx_clk,
rx_rst=dut.qsfp2_mac_1_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp2_mac_2_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp2_mac_2_tx_clk, 6.206, units="ns").start())
self.qsfp2_mac_2 = EthMac(
tx_clk=dut.qsfp2_mac_2_tx_clk,
tx_rst=dut.qsfp2_mac_2_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_tx_axis"),
rx_clk=dut.qsfp2_mac_2_rx_clk,
rx_rst=dut.qsfp2_mac_2_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp2_mac_3_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp2_mac_3_tx_clk, 6.206, units="ns").start())
self.qsfp2_mac_3 = EthMac(
tx_clk=dut.qsfp2_mac_3_tx_clk,
tx_rst=dut.qsfp2_mac_3_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_tx_axis"),
rx_clk=dut.qsfp2_mac_3_rx_clk,
rx_rst=dut.qsfp2_mac_3_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_rx_axis"),
ifg=12,
speed=10e9)
cocotb.start_soon(
Clock(dut.qsfp2_mac_4_rx_clk, 6.206, units="ns").start())
cocotb.start_soon(
Clock(dut.qsfp2_mac_4_tx_clk, 6.206, units="ns").start())
self.qsfp2_mac_4 = EthMac(
tx_clk=dut.qsfp2_mac_4_tx_clk,
tx_rst=dut.qsfp2_mac_4_tx_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_tx_axis"),
rx_clk=dut.qsfp2_mac_4_rx_clk,
rx_rst=dut.qsfp2_mac_4_rx_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_rx_axis"),
ifg=12,
speed=10e9)
dut.btn.setimmediatevalue(0)
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# AXI
self.address_space = AddressSpace()
self.pool = self.address_space.create_pool(0, 0x8000_0000)
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk, dut.rst)
self.address_space.register_region(self.axil_master, 0x10_0000_0000)
self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size)
self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, self.address_space)
self.driver = mqnic.Driver()
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_clock_period = 6.4
eth_speed = 10e9
if eth_int_if_width == 64:
# 10G
eth_clock_period = 6.4
eth_speed = 10e9
elif eth_int_if_width == 128:
# 25G
eth_clock_period = 2.56
eth_speed = 25e9
elif eth_int_if_width == 512:
# 100G
eth_clock_period = 3.102
eth_speed = 100e9
for iface in dut.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
dut.s_axis_stat_tvalid.setimmediatevalue(0)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())