class TB(object): def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.rc.max_payload_size = 0x1 # 256 bytes self.rc.max_read_request_size = 0x2 # 512 bytes self.dev = UltraScalePcieDevice( # configuration options pcie_generation=3, pcie_link_width=8, user_clk_frequency=250e6, alignment="dword", straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=True, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals # Clock and Reset Interface user_clk=dut.clk_250mhz, user_reset=dut.rst_250mhz, # user_lnk_up # sys_clk # sys_clk_gt # sys_reset # phy_rdy_out # Requester reQuest Interface rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num=dut.s_axis_rq_seq_num, pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid, # pcie_rq_tag # pcie_rq_tag_av # pcie_rq_tag_vld # Requester Completion Interface rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=dut.cfg_mgmt_addr, cfg_mgmt_write=dut.cfg_mgmt_write, cfg_mgmt_write_data=dut.cfg_mgmt_write_data, cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, cfg_mgmt_read=dut.cfg_mgmt_read, cfg_mgmt_read_data=dut.cfg_mgmt_read_data, cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, # cfg_mgmt_debug_access # Configuration Status Interface # cfg_phy_link_down # cfg_phy_link_status # cfg_negotiated_width # cfg_current_speed cfg_max_payload=dut.cfg_max_payload, cfg_max_read_req=dut.cfg_max_read_req, # cfg_function_status # cfg_vf_status # cfg_function_power_state # cfg_vf_power_state # cfg_link_power_state # cfg_err_cor_out # cfg_err_nonfatal_out # cfg_err_fatal_out # cfg_local_error_out # cfg_local_error_valid # cfg_rx_pm_state # cfg_tx_pm_state # cfg_ltssm_state # cfg_rcb_status # cfg_obff_enable # cfg_pl_status_change # cfg_tph_requester_enable # cfg_tph_st_mode # cfg_vf_tph_requester_enable # cfg_vf_tph_st_mode # Configuration Received Message Interface # cfg_msg_received # cfg_msg_received_data # cfg_msg_received_type # Configuration Transmit Message Interface # cfg_msg_transmit # cfg_msg_transmit_type # cfg_msg_transmit_data # cfg_msg_transmit_done # Configuration Flow Control Interface cfg_fc_ph=dut.cfg_fc_ph, cfg_fc_pd=dut.cfg_fc_pd, cfg_fc_nph=dut.cfg_fc_nph, cfg_fc_npd=dut.cfg_fc_npd, cfg_fc_cplh=dut.cfg_fc_cplh, cfg_fc_cpld=dut.cfg_fc_cpld, cfg_fc_sel=dut.cfg_fc_sel, # Configuration Control Interface # cfg_hot_reset_in # cfg_hot_reset_out # cfg_config_space_enable # cfg_dsn # cfg_bus_number # cfg_ds_port_number # cfg_ds_bus_number # cfg_ds_device_number # cfg_ds_function_number # cfg_power_state_change_ack # cfg_power_state_change_interrupt cfg_err_cor_in=dut.status_error_cor, cfg_err_uncor_in=dut.status_error_uncor, # cfg_flr_in_process # cfg_flr_done # cfg_vf_flr_in_process # cfg_vf_flr_func_num # cfg_vf_flr_done # cfg_pm_aspm_l1_entry_reject # cfg_pm_aspm_tx_l0s_entry_disable # cfg_req_pm_transition_l23_ready # cfg_link_training_enable # Configuration Interrupt Controller Interface # cfg_interrupt_int # cfg_interrupt_sent # cfg_interrupt_pending cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable=dut.cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=dut. cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable=dut. cfg_interrupt_msi_pending_status_data_enable, cfg_interrupt_msi_pending_status_function_num=dut. cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msix_enable # cfg_interrupt_msix_mask # cfg_interrupt_msix_vf_enable # cfg_interrupt_msix_vf_mask # cfg_interrupt_msix_address # cfg_interrupt_msix_data # cfg_interrupt_msix_int # cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending_status cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, # Configuration Extend Interface # cfg_ext_read_received # cfg_ext_write_received # cfg_ext_register_number # cfg_ext_function_number # cfg_ext_write_data # cfg_ext_write_byte_enable # cfg_ext_read_data # cfg_ext_read_data_valid ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.driver = mqnic.Driver() self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar( 0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar( 2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst) cocotb.start_soon(Clock(dut.sfp_3_rx_clk, 6.4, units="ns").start()) self.sfp_3_source = XgmiiSource(dut.sfp_3_rxd, dut.sfp_3_rxc, dut.sfp_3_rx_clk, dut.sfp_3_rx_rst) cocotb.start_soon(Clock(dut.sfp_3_tx_clk, 6.4, units="ns").start()) self.sfp_3_sink = XgmiiSink(dut.sfp_3_txd, dut.sfp_3_txc, dut.sfp_3_tx_clk, dut.sfp_3_tx_rst) cocotb.start_soon(Clock(dut.sfp_4_rx_clk, 6.4, units="ns").start()) self.sfp_4_source = XgmiiSource(dut.sfp_4_rxd, dut.sfp_4_rxc, dut.sfp_4_rx_clk, dut.sfp_4_rx_rst) cocotb.start_soon(Clock(dut.sfp_4_tx_clk, 6.4, units="ns").start()) self.sfp_4_sink = XgmiiSink(dut.sfp_4_txd, dut.sfp_4_txc, dut.sfp_4_tx_clk, dut.sfp_4_tx_rst) dut.btn.setimmediatevalue(0) dut.i2c_scl_i.setimmediatevalue(1) dut.i2c_sda_i.setimmediatevalue(1) self.loopback_enable = False cocotb.start_soon(self._run_loopback()) async def init(self): self.dut.sfp_1_rx_rst.setimmediatevalue(0) self.dut.sfp_1_tx_rst.setimmediatevalue(0) self.dut.sfp_2_rx_rst.setimmediatevalue(0) self.dut.sfp_2_tx_rst.setimmediatevalue(0) self.dut.sfp_3_rx_rst.setimmediatevalue(0) self.dut.sfp_3_tx_rst.setimmediatevalue(0) self.dut.sfp_4_rx_rst.setimmediatevalue(0) self.dut.sfp_4_tx_rst.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.sfp_1_rx_rst.setimmediatevalue(1) self.dut.sfp_1_tx_rst.setimmediatevalue(1) self.dut.sfp_2_rx_rst.setimmediatevalue(1) self.dut.sfp_2_tx_rst.setimmediatevalue(1) self.dut.sfp_3_rx_rst.setimmediatevalue(1) self.dut.sfp_3_tx_rst.setimmediatevalue(1) self.dut.sfp_4_rx_rst.setimmediatevalue(1) self.dut.sfp_4_tx_rst.setimmediatevalue(1) await FallingEdge(self.dut.rst_250mhz) await Timer(100, 'ns') await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.sfp_1_rx_rst.setimmediatevalue(0) self.dut.sfp_1_tx_rst.setimmediatevalue(0) self.dut.sfp_2_rx_rst.setimmediatevalue(0) self.dut.sfp_2_tx_rst.setimmediatevalue(0) self.dut.sfp_3_rx_rst.setimmediatevalue(0) self.dut.sfp_3_tx_rst.setimmediatevalue(0) self.dut.sfp_4_rx_rst.setimmediatevalue(0) self.dut.sfp_4_tx_rst.setimmediatevalue(0) await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) async def _run_loopback(self): while True: await RisingEdge(self.dut.clk_250mhz) if self.loopback_enable: if not self.sfp_1_sink.empty(): await self.sfp_1_source.send(await self.sfp_1_sink.recv()) if not self.sfp_2_sink.empty(): await self.sfp_2_source.send(await self.sfp_2_sink.recv()) if not self.sfp_3_sink.empty(): await self.sfp_3_source.send(await self.sfp_3_sink.recv()) if not self.sfp_4_sink.empty(): await self.sfp_4_source.send(await self.sfp_4_sink.recv())
class TB(object): def __init__(self, dut): self.dut = dut self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE")) self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.rc.max_payload_size = 0x1 # 256 bytes self.rc.max_read_request_size = 0x2 # 512 bytes self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=True, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals # Clock and Reset Interface user_clk=dut.clk_250mhz, user_reset=dut.rst_250mhz, # user_lnk_up # sys_clk # sys_clk_gt # sys_reset # phy_rdy_out # Requester reQuest Interface rq_entity=dut, rq_name="m_axis_rq", pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, # pcie_rq_tag0 # pcie_rq_tag1 # pcie_rq_tag_av # pcie_rq_tag_vld0 # pcie_rq_tag_vld1 # Requester Completion Interface rc_entity=dut, rc_name="s_axis_rc", # Completer reQuest Interface cq_entity=dut, cq_name="s_axis_cq", # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface cc_entity=dut, cc_name="m_axis_cc", # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=dut.cfg_mgmt_addr, cfg_mgmt_function_number=dut.cfg_mgmt_function_number, cfg_mgmt_write=dut.cfg_mgmt_write, cfg_mgmt_write_data=dut.cfg_mgmt_write_data, cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, cfg_mgmt_read=dut.cfg_mgmt_read, cfg_mgmt_read_data=dut.cfg_mgmt_read_data, cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, # cfg_mgmt_debug_access # Configuration Status Interface # cfg_phy_link_down # cfg_phy_link_status # cfg_negotiated_width # cfg_current_speed cfg_max_payload=dut.cfg_max_payload, cfg_max_read_req=dut.cfg_max_read_req, # cfg_function_status # cfg_vf_status # cfg_function_power_state # cfg_vf_power_state # cfg_link_power_state # cfg_err_cor_out # cfg_err_nonfatal_out # cfg_err_fatal_out # cfg_local_error_out # cfg_local_error_valid # cfg_rx_pm_state # cfg_tx_pm_state # cfg_ltssm_state # cfg_rcb_status # cfg_obff_enable # cfg_pl_status_change # cfg_tph_requester_enable # cfg_tph_st_mode # cfg_vf_tph_requester_enable # cfg_vf_tph_st_mode # Configuration Received Message Interface # cfg_msg_received # cfg_msg_received_data # cfg_msg_received_type # Configuration Transmit Message Interface # cfg_msg_transmit # cfg_msg_transmit_type # cfg_msg_transmit_data # cfg_msg_transmit_done # Configuration Flow Control Interface cfg_fc_ph=dut.cfg_fc_ph, cfg_fc_pd=dut.cfg_fc_pd, cfg_fc_nph=dut.cfg_fc_nph, cfg_fc_npd=dut.cfg_fc_npd, cfg_fc_cplh=dut.cfg_fc_cplh, cfg_fc_cpld=dut.cfg_fc_cpld, cfg_fc_sel=dut.cfg_fc_sel, # Configuration Control Interface # cfg_hot_reset_in # cfg_hot_reset_out # cfg_config_space_enable # cfg_dsn # cfg_bus_number # cfg_ds_port_number # cfg_ds_bus_number # cfg_ds_device_number # cfg_ds_function_number # cfg_power_state_change_ack # cfg_power_state_change_interrupt cfg_err_cor_in=dut.status_error_cor, cfg_err_uncor_in=dut.status_error_uncor, # cfg_flr_in_process # cfg_flr_done # cfg_vf_flr_in_process # cfg_vf_flr_func_num # cfg_vf_flr_done # cfg_pm_aspm_l1_entry_reject # cfg_pm_aspm_tx_l0s_entry_disable # cfg_req_pm_transition_l23_ready # cfg_link_training_enable # Configuration Interrupt Controller Interface # cfg_interrupt_int # cfg_interrupt_sent # cfg_interrupt_pending cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=dut. cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable=dut. cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msix_enable # cfg_interrupt_msix_mask # cfg_interrupt_msix_vf_enable # cfg_interrupt_msix_vf_mask # cfg_interrupt_msix_address # cfg_interrupt_msix_data # cfg_interrupt_msix_int # cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending_status cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, # Configuration Extend Interface # cfg_ext_read_received # cfg_ext_write_received # cfg_ext_register_number # cfg_ext_function_number # cfg_ext_write_data # cfg_ext_write_byte_enable # cfg_ext_read_data # cfg_ext_read_data_valid ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.driver = mqnic.Driver(self.rc) self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) cocotb.fork(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) cocotb.fork(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) cocotb.fork(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) cocotb.fork(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) cocotb.fork(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) cocotb.fork(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) cocotb.fork(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) cocotb.fork(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) cocotb.fork(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) cocotb.fork(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) cocotb.fork(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) cocotb.fork(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) cocotb.fork(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) cocotb.fork(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) cocotb.fork(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) dut.qsfp0_rx_error_count_1.setimmediatevalue(0) dut.qsfp0_rx_error_count_2.setimmediatevalue(0) dut.qsfp0_rx_error_count_3.setimmediatevalue(0) dut.qsfp0_rx_error_count_4.setimmediatevalue(0) dut.qsfp1_rx_error_count_1.setimmediatevalue(0) dut.qsfp1_rx_error_count_2.setimmediatevalue(0) dut.qsfp1_rx_error_count_3.setimmediatevalue(0) dut.qsfp1_rx_error_count_4.setimmediatevalue(0) dut.qspi_dq_i.setimmediatevalue(0) self.cms_ram = AxiLiteRam(dut, "m_axil_cms", dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256 * 1024) self.loopback_enable = False cocotb.fork(self._run_loopback()) async def init(self): self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.qsfp0_rx_rst_1.setimmediatevalue(1) self.dut.qsfp0_tx_rst_1.setimmediatevalue(1) self.dut.qsfp0_rx_rst_2.setimmediatevalue(1) self.dut.qsfp0_tx_rst_2.setimmediatevalue(1) self.dut.qsfp0_rx_rst_3.setimmediatevalue(1) self.dut.qsfp0_tx_rst_3.setimmediatevalue(1) self.dut.qsfp0_rx_rst_4.setimmediatevalue(1) self.dut.qsfp0_tx_rst_4.setimmediatevalue(1) self.dut.qsfp1_rx_rst_1.setimmediatevalue(1) self.dut.qsfp1_tx_rst_1.setimmediatevalue(1) self.dut.qsfp1_rx_rst_2.setimmediatevalue(1) self.dut.qsfp1_tx_rst_2.setimmediatevalue(1) self.dut.qsfp1_rx_rst_3.setimmediatevalue(1) self.dut.qsfp1_tx_rst_3.setimmediatevalue(1) self.dut.qsfp1_rx_rst_4.setimmediatevalue(1) self.dut.qsfp1_tx_rst_4.setimmediatevalue(1) await FallingEdge(self.dut.rst_250mhz) await Timer(100, 'ns') await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) async def _run_loopback(self): while True: await RisingEdge(self.dut.clk_250mhz) if self.loopback_enable: if not self.qsfp0_1_sink.empty(): await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv()) if not self.qsfp0_2_sink.empty(): await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv()) if not self.qsfp0_3_sink.empty(): await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv()) if not self.qsfp0_4_sink.empty(): await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv()) if not self.qsfp1_1_sink.empty(): await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv()) if not self.qsfp1_2_sink.empty(): await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv()) if not self.qsfp1_3_sink.empty(): await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv()) if not self.qsfp1_4_sink.empty(): await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv())
class TB(object): def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.rc.max_payload_size = 0x1 # 256 bytes self.rc.max_read_request_size = 0x2 # 512 bytes self.dev = S10PcieDevice( # configuration options pcie_generation=3, # pcie_link_width=8, # pld_clk_frequency=250e6, l_tile=False, # signals # Clock and reset # npor=dut.npor, # pin_perst=dut.pin_perst, # ninit_done=dut.ninit_done, # pld_clk_inuse=dut.pld_clk_inuse, # pld_core_ready=dut.pld_core_ready, reset_status=dut.rst_250mhz, # clr_st=dut.clr_st, # refclk=dut.refclk, coreclkout_hip=dut.clk_250mhz, # RX interface rx_bus=S10RxBus.from_prefix(dut, "rx_st"), # TX interface tx_bus=S10TxBus.from_prefix(dut, "tx_st"), # TX flow control tx_ph_cdts=dut.tx_ph_cdts, tx_pd_cdts=dut.tx_pd_cdts, tx_nph_cdts=dut.tx_nph_cdts, tx_npd_cdts=dut.tx_npd_cdts, tx_cplh_cdts=dut.tx_cplh_cdts, tx_cpld_cdts=dut.tx_cpld_cdts, tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed, tx_data_cdts_consumed=dut.tx_data_cdts_consumed, tx_cdts_type=dut.tx_cdts_type, tx_cdts_data_value=dut.tx_cdts_data_value, # Hard IP status # int_status=dut.int_status, # int_status_common=dut.int_status_common, # derr_cor_ext_rpl=dut.derr_cor_ext_rpl, # derr_rpl=dut.derr_rpl, # derr_cor_ext_rcv=dut.derr_cor_ext_rcv, # derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv, # rx_par_err=dut.rx_par_err, # tx_par_err=dut.tx_par_err, # ltssmstate=dut.ltssmstate, # link_up=dut.link_up, # lane_act=dut.lane_act, # currentspeed=dut.currentspeed, # Power management # pm_linkst_in_l1=dut.pm_linkst_in_l1, # pm_linkst_in_l0s=dut.pm_linkst_in_l0s, # pm_state=dut.pm_state, # pm_dstate=dut.pm_dstate, # apps_pm_xmt_pme=dut.apps_pm_xmt_pme, # apps_ready_entr_l23=dut.apps_ready_entr_l23, # apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff, # app_init_rst=dut.app_init_rst, # app_xfer_pending=dut.app_xfer_pending, # Interrupt interface app_msi_req=dut.app_msi_req, app_msi_ack=dut.app_msi_ack, app_msi_tc=dut.app_msi_tc, app_msi_num=dut.app_msi_num, app_msi_func_num=dut.app_msi_func_num, # app_int_sts=dut.app_int_sts, # Error interface # app_err_valid=dut.app_err_valid, # app_err_hdr=dut.app_err_hdr, # app_err_info=dut.app_err_info, # app_err_func_num=dut.app_err_func_num, # Configuration output tl_cfg_func=dut.tl_cfg_func, tl_cfg_add=dut.tl_cfg_add, tl_cfg_ctl=dut.tl_cfg_ctl, # Configuration extension bus # ceb_req=dut.ceb_req, # ceb_ack=dut.ceb_ack, # ceb_addr=dut.ceb_addr, # ceb_din=dut.ceb_din, # ceb_dout=dut.ceb_dout, # ceb_wr=dut.ceb_wr, # ceb_cdm_convert_data=dut.ceb_cdm_convert_data, # ceb_func_num=dut.ceb_func_num, # ceb_vf_num=dut.ceb_vf_num, # ceb_vf_active=dut.ceb_vf_active, # Hard IP reconfiguration interface # hip_reconfig_clk=dut.hip_reconfig_clk, # hip_reconfig_address=dut.hip_reconfig_address, # hip_reconfig_read=dut.hip_reconfig_read, # hip_reconfig_readdata=dut.hip_reconfig_readdata, # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid, # hip_reconfig_write=dut.hip_reconfig_write, # hip_reconfig_writedata=dut.hip_reconfig_writedata, # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest, ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.driver = mqnic.Driver() self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) # Ethernet cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) # dut.qsfp0_i2c_scl_i.setimmediatevalue(1) # dut.qsfp0_i2c_sda_i.setimmediatevalue(1) # dut.qsfp0_intr_n.setimmediatevalue(1) # dut.qsfp0_mod_prsnt_n.setimmediatevalue(0) # dut.qsfp0_rx_error_count_0.setimmediatevalue(0) # dut.qsfp0_rx_error_count_1.setimmediatevalue(0) # dut.qsfp0_rx_error_count_2.setimmediatevalue(0) # dut.qsfp0_rx_error_count_3.setimmediatevalue(0) # dut.qsfp1_i2c_scl_i.setimmediatevalue(1) # dut.qsfp1_i2c_sda_i.setimmediatevalue(1) # dut.qsfp1_intr_n.setimmediatevalue(1) # dut.qsfp1_mod_prsnt_n.setimmediatevalue(0) # dut.qsfp1_rx_error_count_0.setimmediatevalue(0) # dut.qsfp1_rx_error_count_1.setimmediatevalue(0) # dut.qsfp1_rx_error_count_2.setimmediatevalue(0) # dut.qsfp1_rx_error_count_3.setimmediatevalue(0) # dut.qspi_dq_i.setimmediatevalue(0) self.loopback_enable = False cocotb.start_soon(self._run_loopback()) async def init(self): self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.qsfp0_rx_rst_1.setimmediatevalue(1) self.dut.qsfp0_tx_rst_1.setimmediatevalue(1) self.dut.qsfp0_rx_rst_2.setimmediatevalue(1) self.dut.qsfp0_tx_rst_2.setimmediatevalue(1) self.dut.qsfp0_rx_rst_3.setimmediatevalue(1) self.dut.qsfp0_tx_rst_3.setimmediatevalue(1) self.dut.qsfp0_rx_rst_4.setimmediatevalue(1) self.dut.qsfp0_tx_rst_4.setimmediatevalue(1) self.dut.qsfp1_rx_rst_1.setimmediatevalue(1) self.dut.qsfp1_tx_rst_1.setimmediatevalue(1) self.dut.qsfp1_rx_rst_2.setimmediatevalue(1) self.dut.qsfp1_tx_rst_2.setimmediatevalue(1) self.dut.qsfp1_rx_rst_3.setimmediatevalue(1) self.dut.qsfp1_tx_rst_3.setimmediatevalue(1) self.dut.qsfp1_rx_rst_4.setimmediatevalue(1) self.dut.qsfp1_tx_rst_4.setimmediatevalue(1) await FallingEdge(self.dut.rst_250mhz) await Timer(100, 'ns') await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True) async def _run_loopback(self): while True: await RisingEdge(self.dut.clk_250mhz) if self.loopback_enable: if not self.qsfp0_1_sink.empty(): await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv()) if not self.qsfp0_2_sink.empty(): await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv()) if not self.qsfp0_3_sink.empty(): await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv()) if not self.qsfp0_4_sink.empty(): await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv()) if not self.qsfp1_1_sink.empty(): await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv()) if not self.qsfp1_2_sink.empty(): await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv()) if not self.qsfp1_3_sink.empty(): await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv()) if not self.qsfp1_4_sink.empty(): await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv())
class TB(object): def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk_250mhz, 4, units="ns").start()) # AXI self.address_space = AddressSpace() self.pool = self.address_space.create_pool(0, 0x8000_0000) self.axil_master = AxiLiteMaster( AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_250mhz, dut.rst_250mhz) self.address_space.register_region(self.axil_master, 0x10_0000_0000) self.hw_regs = self.address_space.create_window( 0x10_0000_0000, self.axil_master.size) self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_250mhz, dut.rst_250mhz, self.address_space) self.driver = mqnic.Driver() # Ethernet cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start()) dut.sfp_drp_rst.setimmediatevalue(0) dut.sfp_drp_do.setimmediatevalue(0) dut.sfp_drp_rdy.setimmediatevalue(0) dut.sfp0_rx_error_count.setimmediatevalue(0) dut.sfp1_rx_error_count.setimmediatevalue(0) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) dut.i2c_scl_i.setimmediatevalue(1) dut.i2c_sda_i.setimmediatevalue(1) self.loopback_enable = False cocotb.start_soon(self._run_loopback()) async def init(self): self.dut.rst_250mhz.setimmediatevalue(0) self.dut.sfp0_rx_rst.setimmediatevalue(0) self.dut.sfp0_tx_rst.setimmediatevalue(0) self.dut.sfp1_rx_rst.setimmediatevalue(0) self.dut.sfp1_tx_rst.setimmediatevalue(0) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.rst_250mhz.value = 1 self.dut.sfp0_rx_rst.setimmediatevalue(1) self.dut.sfp0_tx_rst.setimmediatevalue(1) self.dut.sfp1_rx_rst.setimmediatevalue(1) self.dut.sfp1_tx_rst.setimmediatevalue(1) await RisingEdge(self.dut.clk_250mhz) await RisingEdge(self.dut.clk_250mhz) self.dut.rst_250mhz.value = 0 self.dut.sfp0_rx_rst.setimmediatevalue(0) self.dut.sfp0_tx_rst.setimmediatevalue(0) self.dut.sfp1_rx_rst.setimmediatevalue(0) self.dut.sfp1_tx_rst.setimmediatevalue(0) async def _run_loopback(self): while True: await RisingEdge(self.dut.clk_250mhz) if self.loopback_enable: if not self.sfp0_sink.empty(): await self.sfp0_source.send(await self.sfp0_sink.recv()) if not self.sfp1_sink.empty(): await self.sfp1_source.send(await self.sfp1_sink.recv())