def _stopDetection(self):
yield RisingEdge(self.clk)
while True:
prev = int(self.sda)
yield RisingEdge(self.clk)
if prev == 0 and int(self.sda) == 1:
if int(self.scl) == 1:
self.event_Stop.set()
self.listOp.append(STOP())
# check sequence...
for (op, ref) in zip(self.listOp, self.refListOp):
if isinstance(ref, START) and isinstance(op, START):
pass
elif isinstance(ref, STOP) and isinstance(op, STOP):
pass
elif isinstance(ref, ACK) and isinstance(op, ACK):
pass
elif isinstance(ref, NACK) and isinstance(op, NACK):
pass
elif (isinstance(ref, WRITE) or isinstance(ref, READ)) and isinstance(op, DATA):
if ref.data != op.data:
print("ref ", hex(ref.data), " op ", hex(op.data))
assertEquals(ref.data , op.data , "Analyser data ERROR")
else:
assertEquals(True , False , "%s is not equal to %s" % (ref, op))
def checkCtrlReadedBytes(dut, queue):
for i in range(0,200):
while True:
yield RisingEdge(dut.clk)
if int(dut.io_uart_read_valid) == 1 :
break
assertEquals(queue.get(), dut.io_uart_read_payload,"io_uart_read_payload")
def onOutput(self,payload,dummy):
if self.queues[self.nextPort].empty():
raise TestFailure("ArbiterRoundRobin Empty queue")
assertEquals(payload,self.queues[self.nextPort].get(),"ArbiterRoundRobin payload error")
self.counter += 1
self.previousPort = self.nextPort
self.nextPort = -1
def onOutput(self,payload,dummy):
if self.queues[self.nextPort].empty():
raise TestFailure("ArbiterLowIdPortFragmentLockFirst Empty queue")
assertEquals(payload.fragment,self.queues[self.nextPort].get(),"ArbiterLowIdPortFragmentLockFirst payload error")
self.counter += 1
if payload.last == 1:
self.nextPort = -1
def test_fibonacci_left(dut):
dut.log.info("Cocotb test LFSR fibonacci left")
clockDomain = ClockDomain(dut.clk, 500, None , RESET_ACTIVE_LEVEL.LOW)
# Start clock
cocotb.fork(clockDomain.start())
# Init IO and wait the end of the reset
dut.io_fib_inc <= 0
dut.io_fib_init <= 0
dut.io_fib_seed <= 0
dut.io_fib_rightLeft <= LFSR_SHIFT_DIR.SHIFT_LEFT
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
# init LFSR
widthData = 32
initValue = randInt(0, 2**widthData)
dut.io_fib_init <= 1
dut.io_fib_seed <= initValue
lfsr = FibonacciLFSR(initValue, [0,2,3,5,10], widthData, LFSR_SHIFT_DIR.SHIFT_LEFT)
yield RisingEdge(dut.clk)
dut.io_fib_init <= 0
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
for _ in range(0,10):
dut.io_fib_inc <= 1
yield RisingEdge(dut.clk)
dut.io_fib_inc <= 0
yield RisingEdge(dut.clk)
lfsr.getRand()
realResult = int(dut.io_fib_result)
assertEquals(lfsr.state, realResult, "LFSR Fibonacci Left - Comparaison Error python : %s - %s : hdl" % (hex(lfsr.state), hex(realResult)))
yield RisingEdge(dut.clk)
dut.io_fib_inc <= 0
yield RisingEdge(dut.clk)
dut.log.info("Cocotb test LFSR fibonacci left")
def test_galois_right(dut):
dut.log.info("Cocotb test right LFSR Galois")
clockDomain = ClockDomain(dut.clk, 500, None , RESET_ACTIVE_LEVEL.LOW)
# Start clock
cocotb.fork(clockDomain.start())
# Init IO and wait the end of the reset
dut.io_gal_inc <= 0
dut.io_gal_init <= 0
dut.io_gal_seed <= 0
dut.io_gal_rightLeft <= LFSR_SHIFT_DIR.SHIFT_RIGHT
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
# init LFSR
widthData = 16
initValue = randInt(0, 2**widthData)
dut.io_gal_init <= 1
dut.io_gal_seed <= initValue
lfsr = GaloisLFSR(initValue, [1,2], widthData, LFSR_SHIFT_DIR.SHIFT_RIGHT)
yield RisingEdge(dut.clk)
dut.io_gal_init <= 0
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
for _ in range(0,10):
dut.io_gal_inc <= 1
yield RisingEdge(dut.clk)
dut.io_gal_inc <= 0
yield RisingEdge(dut.clk)
lfsr.getRand()
realResult = int(dut.io_gal_result)
assertEquals(lfsr.state, realResult, "LFSR Galois Right - Comparaison Error python : %s - %s : hdl" % (hex(lfsr.state), hex(realResult)))
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
dut.log.info("Cocotb test right LFSR galois")
def rsp(dut,queue):
readyRandomizer = BoolRandomizer()
dut.io_master0_ready <= 0
for i in range(0,1000):
while True:
yield RisingEdge(dut.io_clkB)
dut.io_master0_ready <= readyRandomizer.get()
if int(dut.io_master0_valid) == 1 and int(dut.io_master0_ready) == 1:
break
pop = queue.get()
assertEquals(pop.a, dut.io_master0_payload_a,"io_master0_payload_a")
assertEquals(pop.b, dut.io_master0_payload_b, "io_master0_payload_b")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
table = [0x01234567,0x12345670,0x10293857,0x0abcfe23,0x02938571,0xabcfe230,0x717833aa,0x17833aa6]
for i in xrange(1000):
dut.address <= random.getrandbits(3)
yield Timer(10)
assertEquals(dut.data,table[int(dut.address)],"1")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
ref = Ref(dut)
for i in range(0,1000):
randSignal(dut.enable)
yield RisingEdge(dut.clk)
assertEquals(ref.getGray(),dut.gray,"gray")
dut.log.info("Cocotb test done")
def run(self):
dut = self.dut
cocotb.fork(
StreamRandomizer("streamFlowArbiterInputStream",
self.onInputStream, None, dut, dut.clk))
cocotb.fork(
FlowRandomizer("streamFlowArbiterInputFlow", self.onInputFlow,
None, dut, dut.clk))
while not (self.inputFlowCounter > 1000
and self.inputStreamCounter > 1000):
yield RisingEdge(dut.clk)
if int(dut.streamFlowArbiterOutput_valid) == 1:
if int(dut.streamFlowArbiterInputFlow_valid) == 1:
assertEquals(dut.streamFlowArbiterOutput_payload,
dut.streamFlowArbiterInputFlow_payload,
"StreamFlowArbiter payload error")
assertEquals(0, dut.streamFlowArbiterInputStream_ready,
"StreamFlowArbiter arbitration error")
self.inputFlowCounter += 1
else:
assertEquals(dut.streamFlowArbiterOutput_payload,
dut.streamFlowArbiterInputStream_payload,
"StreamFlowArbiter payload error")
assertEquals(0, dut.streamFlowArbiterInputFlow_valid,
"StreamFlowArbiter arbitration error")
self.inputStreamCounter += 1
def pop(self):
dut = self.dut
queue = self.queue
readyRandomizer = BoolRandomizer()
dut.io_master0_ready <= 0
for i in range(0,1000):
while True:
yield RisingEdge(dut.clk)
dut.io_master0_ready <= readyRandomizer.get()
if int(dut.io_master0_valid) == 1 and int(dut.io_master0_ready) == 1:
break
pop = queue.get()
assertEquals(pop.a, dut.io_master0_payload_a,"io_master0_payload_a")
assertEquals(pop.b, dut.io_master0_payload_b, "io_master0_payload_b")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, None))
for i in range(0,1000):
randSignal(dut.io_inSIntA)
randSignal(dut.io_inSIntB)
yield Timer(1000)
ref = Ref(dut)
assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt")
dut.log.info("Cocotb test done")
def pop(self):
dut = self.dut
queue = self.queue
readyRandomizer = BoolRandomizer()
dut.io_master0_ready <= 0
for i in range(0,1000):
while True:
yield RisingEdge(dut.clk)
dut.io_master0_ready <= readyRandomizer.get()
if int(dut.io_master0_valid) == 1 and int(dut.io_master0_ready) == 1:
break
pop = queue.get()
assertEquals(pop.a, dut.io_master0_payload_a,"io_master0_payload_a")
assertEquals(pop.b, dut.io_master0_payload_b, "io_master0_payload_b")
def test1(dut):
dut.log.info("Cocotb test boot")
cocotb.fork(genClkReset(dut))
yield Timer(20000)
print "yolo" + str(dut.counter)
assertEquals(dut.counter,3,"Missmatch")
dut.aReset <= 1
yield Timer(5)
dut.aReset <= 0
yield Timer(40000)
print "yolo" + str(dut.counter)
assertEquals(dut.counter,3+5,"Missmatch")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
for i in range(0, 1000):
randSignal(dut.io_conds_0)
randSignal(dut.io_conds_1)
randSignal(dut.io_conds_2)
randSignal(dut.io_conds_3)
randSignal(dut.io_conds_4)
randSignal(dut.io_conds_5)
randSignal(dut.io_conds_6)
randSignal(dut.io_conds_7)
randSignal(dut.io_inAA_0_a)
randSignal(dut.io_inAA_0_c)
randSignal(dut.io_inAA_0_b)
randSignal(dut.io_inAA_0_d)
randSignal(dut.io_inAA_1_a)
randSignal(dut.io_inAA_1_c)
randSignal(dut.io_inAA_1_b)
randSignal(dut.io_inAA_1_d)
randSignal(dut.io_inAA_2_a)
randSignal(dut.io_inAA_2_c)
randSignal(dut.io_inAA_2_b)
randSignal(dut.io_inAA_2_d)
randSignal(dut.io_inA_0_a)
randSignal(dut.io_inA_0_c)
yield Timer(1000)
ref = Ref(dut)
assertEquals(ref.io_outAA_a, dut.io_outAA_a, "io_outAA_a")
assertEquals(ref.io_outAA_b, dut.io_outAA_b, "io_outAA_b")
assertEquals(ref.io_outAA_c, dut.io_outAA_c, "io_outAA_c")
assertEquals(ref.io_outAA_d, dut.io_outAA_d, "io_outAA_d")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
table = [
0x01234567, 0x12345670, 0x10293857, 0x0abcfe23, 0x02938571, 0xabcfe230,
0x717833aa, 0x17833aa6
]
for i in range(1000):
dut.address <= random.getrandbits(3)
yield Timer(10)
assertEquals(dut.data, table[int(dut.address)], "1")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
cocotb.fork(genClkReset(dut))
yield Timer(20000)
print "yolo" + str(dut.counter)
assertEquals(dut.counter, 3, "Missmatch")
dut.aReset <= 1
yield Timer(5)
dut.aReset <= 0
yield Timer(40000)
print "yolo" + str(dut.counter)
assertEquals(dut.counter, 3 + 5, "Missmatch")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
outA_ref = 0
outB_ref = 0
for i in range(0,1000):
randSignal(dut.io_inA)
randSignal(dut.io_inB)
yield RisingEdge(dut.clk)
assertEquals(outA_ref,dut.io_outA,"io_outA")
assertEquals(outB_ref, dut.io_outB, "io_outB")
outA_ref = truncUInt(outA_ref + int(dut.io_inA), dut.io_outA)
outB_ref = truncUInt(outB_ref + int(dut.io_inB), dut.io_outB)
dut.log.info("Cocotb test done")
def driveAndCheck(dut,header,value,valueWidth,pin):
assert(valueWidth % 8 == 0)
for h in header:
yield sendCmdRandomTiming(dut,ord(h))
for i in range(int(valueWidth/8)):
yield sendCmdRandomTiming(dut,(value >> (i*8)) & 0xFF)
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
assertEquals(pin, value,pin._name + " wasn't loaded correctly")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
#random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, None))
for i in range(0, 1000):
randSignal(dut.io_inSIntA)
randSignal(dut.io_inSIntB)
yield Timer(1000)
ref = Ref(dut)
assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt")
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
#random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
while True:
yield RisingEdge(dut.clk)
if int(dut.io_internalClkCounter) == 2:
break
counter = 3
for i in range(0,1000):
yield RisingEdge(dut.clk)
yield RisingEdge(dut.clk)
assertEquals(counter, dut.io_internalClkCounter, "io_internalClkCounter")
counter = truncUInt(counter + 1, dut.io_internalClkCounter)
dut.log.info("Cocotb test done")
def testAESCore(dut):
dut.log.info("Cocotb test AES Core Start")
from cocotblib.misc import cocotbXHack
cocotbXHack()
helperAES = AESCoreHelper(dut)
clockDomain = ClockDomain(helperAES.io.clk, 200, helperAES.io.resetn,
RESET_ACTIVE_LEVEL.LOW)
# Start clock
cocotb.fork(clockDomain.start())
# Init IO and wait the end of the reset
helperAES.io.init()
yield clockDomain.event_endReset.wait()
# start monitoring the Valid signal
helperAES.io.rsp.startMonitoringValid(helperAES.io.clk)
key = 0x2b7e151628aed2a6abf7158809cf4f3c
data = 0x6bc1bee22e409f96e93d7e117393172a
# Encrpytion
helperAES.io.cmd.valid <= 1
helperAES.io.cmd.payload.key <= key
helperAES.io.cmd.payload.block <= data
helperAES.io.cmd.payload.enc <= 1 # do an encryption
# Wait the end of the process and read the result
yield helperAES.io.rsp.event_valid.wait()
rtlEncryptedBlock = int(helperAES.io.rsp.event_valid.data.block)
#print("RTL encrypted", hex(rtlEncryptedBlock))
helperAES.io.cmd.valid <= 0
yield RisingEdge(helperAES.io.clk)
# expected result:
assertEquals(0x3ad77bb40d7a3660a89ecaf32466ef97, rtlEncryptedBlock,
"Encryption data wrong ")
dut.log.info("Cocotb test AES Core End")
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, None))
for i in range(0,1000):
randSignal(dut.io_conds_0)
randSignal(dut.io_conds_1)
randSignal(dut.io_conds_2)
randSignal(dut.io_conds_3)
randSignal(dut.io_conds_4)
randSignal(dut.io_conds_5)
randSignal(dut.io_conds_6)
randSignal(dut.io_conds_7)
randSignal(dut.io_data_0 )
randSignal(dut.io_data_1 )
randSignal(dut.io_data_2 )
randSignal(dut.io_data_3 )
randSignal(dut.io_data_4 )
randSignal(dut.io_data_5 )
randSignal(dut.io_data_6 )
randSignal(dut.io_data_7 )
randSignal(dut.io_data_8 )
randSignal(dut.io_data_9 )
randSignal(dut.io_data_10)
randSignal(dut.io_data_11)
yield RisingEdge(dut.clk)
ref = Ref(dut)
assertEquals(ref.io_outDefault,dut.io_outDefault,"io_outDefault")
assertEquals(ref.io_outComplex, dut.io_outComplex, "io_outComplex")
yield Timer(1)
assertEquals(ref.io_outComplex, dut.io_outRegComplex, "io_outRegComplex")
dut.log.info("Cocotb test done")
def loop(self):
dut = self.dut
while True:
yield RisingEdge(dut.clk)
assertEquals(dut.io_nonStopWrited,truncUInt(int(dut.io_bus_w_payload_data) >> 4,dut.io_nonStopWrited),"io_nonStopWrited")
if int(dut.io_bus_r_valid) & int(dut.io_bus_r_ready) == 1:
if self.readAddresses.empty():
raise TestFailure("FAIL readAddresses is empty")
addr = self.readAddresses.get()
if addr == 9:
assertEquals(dut.io_bus_r_payload_data,self.regA << 10,"io_bus_r_payload_data")
if addr == 7:
assertEquals(dut.io_bus_r_payload_data,self.regB << 10,"io_bus_r_payload_data")
if addr == 2:
self.regB = 33
if int(dut.io_bus_ar_valid) & int(dut.io_bus_ar_ready) == 1:
addr = int(dut.io_bus_ar_payload_addr)
self.readAddresses.put(addr)
if (int(dut.io_bus_aw_valid) & int(dut.io_bus_aw_ready) & int(dut.io_bus_w_valid) & int(dut.io_bus_w_ready)) == 1:
addr = int(dut.io_bus_aw_payload_addr)
if addr == 9:
self.regA = truncUInt(int(dut.io_bus_w_payload_data) >> 10,20)
if addr == 7:
self.regB = truncUInt(int(dut.io_bus_w_payload_data) >> 10,20)
if addr == 15:
self.regA = 11
def genWriteRsp(self):
if len(self.writeCmds) != 0:
if not self.writeRspIdleRand.get():
return None
cmd = self.writeCmds[0]
beatCount = cmd.len + 1
if len(self.writeDatas) >= beatCount:
datas = self.writeDatas[0:beatCount - 1]
#Check it
masterWrite = next(write
for write in self.idToWrites[cmd.hid & 0xF]
if write.addr >> 10 == self.hid)
assertEquals(cmd.addr, masterWrite.addr, "write cmd missmatch")
assertEquals(cmd.len, masterWrite.len, "write cmd missmatch")
for data, dataRef in zip(datas, masterWrite.linkedDatas):
assertEquals(data.data, dataRef.data,
"write data missmatch")
#Clean
self.writeCmds = self.writeCmds[1:]
self.writeDatas = self.writeDatas[beatCount:]
self.idToWrites[cmd.hid & 0xF].remove(masterWrite)
#Answer
trans = Transaction()
trans.hid = cmd.hid
trans.resp = 0
return trans
return None
def loop(self):
dut = self.dut
while True:
yield RisingEdge(dut.clk)
assertEquals(dut.io_nonStopWrited,truncUInt(int(dut.io_bus_w_payload_data) >> 4,dut.io_nonStopWrited),"io_nonStopWrited")
if int(dut.io_bus_r_valid) & int(dut.io_bus_r_ready) == 1:
if self.readAddresses.empty():
raise TestFailure("FAIL readAddresses is empty")
addr = self.readAddresses.get()
if addr == 9:
assertEquals(dut.io_bus_r_payload_data,self.regA << 10,"io_bus_r_payload_data")
if addr == 7:
assertEquals(dut.io_bus_r_payload_data,self.regB << 10,"io_bus_r_payload_data")
if addr == 2:
self.regB = 33
if int(dut.io_bus_ar_valid) & int(dut.io_bus_ar_ready) == 1:
addr = int(dut.io_bus_ar_payload_addr)
self.readAddresses.put(addr)
if (int(dut.io_bus_aw_valid) & int(dut.io_bus_aw_ready) & int(dut.io_bus_w_valid) & int(dut.io_bus_w_ready)) == 1:
addr = int(dut.io_bus_aw_payload_addr)
if addr == 9:
self.regA = truncUInt(int(dut.io_bus_w_payload_data) >> 10,20)
if addr == 7:
self.regB = truncUInt(int(dut.io_bus_w_payload_data) >> 10,20)
if addr == 15:
self.regA = 11
def run(self):
dut = self.dut
cocotb.fork(StreamRandomizer("streamFlowArbiterInputStream", self.onInputStream, None, dut, dut.clk))
cocotb.fork(FlowRandomizer("streamFlowArbiterInputFlow", self.onInputFlow, None, dut, dut.clk))
while not (self.inputFlowCounter > 1000 and self.inputStreamCounter > 1000):
yield RisingEdge(dut.clk)
if int(dut.streamFlowArbiterOutput_valid) == 1:
if int(dut.streamFlowArbiterInputFlow_valid) == 1:
assertEquals(dut.streamFlowArbiterOutput_payload,dut.streamFlowArbiterInputFlow_payload,"StreamFlowArbiter payload error")
assertEquals(0, dut.streamFlowArbiterInputStream_ready, "StreamFlowArbiter arbitration error")
self.inputFlowCounter += 1
else:
assertEquals(dut.streamFlowArbiterOutput_payload,dut.streamFlowArbiterInputStream_payload,"StreamFlowArbiter payload error")
assertEquals(0, dut.streamFlowArbiterInputFlow_valid, "StreamFlowArbiter arbitration error")
self.inputStreamCounter += 1
def stim(self):
ahb = self.ahb
readIncoming = False
while True:
yield RisingEdge(self.clk)
if int(self.ahb.HREADY) == 1:
if readIncoming:
if self.buffer.empty():
raise TestFailure("Empty buffer ??? ")
bufferData = self.buffer.get()
for i in range(byteOffset, byteOffset + size):
assertEquals((int(ahb.HRDATA) >>
(i * 8)) & 0xFF, (bufferData >>
(i * 8)) & 0xFF,
"AHB master read checker faild %x " %
(int(ahb.HADDR)))
self.counter += 1
# cocotb.log.info("POP " + str(self.buffer.qsize()))
readIncoming = int(ahb.HTRANS) >= 2 and int(ahb.HWRITE) == 0
size = 1 << int(ahb.HSIZE)
byteOffset = int(ahb.HADDR) % (len(ahb.HWDATA) / 8)
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
for i in range(0, 1000):
randSignal(dut.io_inSFix_0)
randSignal(dut.io_inSFix_1)
randSignal(dut.io_inBundleA_a_sfix)
randSignal(dut.io_inSFix2)
yield Timer(1000)
ref = Ref(dut)
assertEquals(ref.io_outSFix_0, dut.io_outSFix_0, "io_outSFix_0")
assertEquals(ref.io_outSFix_1, dut.io_outSFix_1, "io_outSFix_1")
assertEquals(ref.io_outSFix2, dut.io_outSFix2, "io_outSFix2")
assertEquals(ref.io_outBundleA_a_sfix, dut.io_outBundleA_a_sfix,
"io_outBundleA_a_sfix")
dut.log.info("Cocotb test done")
def onReadRsp(self, trans):
queue = self.readMonitorQueues[trans.hid - self.hid * 4]
task = queue.queue[0]
if task.addr != 1 << 12:
assertEquals(trans.data,task.addr + task.progress,"Readed value is wrong")
else:
assertEquals(trans.resp, 3, "yep")
task.progress += 1
if task.progress == task.len + 1:
# print("Master FINISH %d %x" % (task.hid,task.addr))
assertEquals(trans.last, 1, "Should be last read")
queue.get()
self.readCounter += 1
self.updateDoFinish()
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
for i in range(0,1000):
randSignal(dut.io_conds_0)
randSignal(dut.io_conds_1)
randSignal(dut.io_conds_2)
randSignal(dut.io_conds_3)
randSignal(dut.io_conds_4)
randSignal(dut.io_conds_5)
randSignal(dut.io_conds_6)
randSignal(dut.io_conds_7)
randSignal(dut.io_inAA_0_a)
randSignal(dut.io_inAA_0_c)
randSignal(dut.io_inAA_0_b)
randSignal(dut.io_inAA_0_d)
randSignal(dut.io_inAA_1_a)
randSignal(dut.io_inAA_1_c)
randSignal(dut.io_inAA_1_b)
randSignal(dut.io_inAA_1_d)
randSignal(dut.io_inAA_2_a)
randSignal(dut.io_inAA_2_c)
randSignal(dut.io_inAA_2_b)
randSignal(dut.io_inAA_2_d)
randSignal(dut.io_inA_0_a)
randSignal(dut.io_inA_0_c)
yield Timer(1000)
ref = Ref(dut)
assertEquals(ref.io_outAA_a, dut.io_outAA_a, "io_outAA_a")
assertEquals(ref.io_outAA_b, dut.io_outAA_b, "io_outAA_b")
assertEquals(ref.io_outAA_c, dut.io_outAA_c, "io_outAA_c")
assertEquals(ref.io_outAA_d, dut.io_outAA_d, "io_outAA_d")
dut.log.info("Cocotb test done")
def loop(self):
dut = self.dut
while True:
yield RisingEdge(dut.clk)
assertEquals(
dut.io_nonStopWrited,
truncUInt(
int(dut.io_bus_w_payload_data) >> 4, dut.io_nonStopWrited),
"io_nonStopWrited")
# when read to addr=2 and write to addr=7 happen at the same cycle
# the former takes precedence
regBassigned = False
if int(dut.io_bus_r_valid) & int(dut.io_bus_r_ready) == 1:
if self.readAddresses.empty():
raise TestFailure("FAIL readAddresses is empty")
addr = self.readAddresses.get()
if addr == 9:
assertEquals(dut.io_bus_r_payload_data, self.regA << 10,
"io_bus_r_payload_data")
if addr == 7:
assertEquals(dut.io_bus_r_payload_data, self.regB << 10,
"io_bus_r_payload_data")
if addr == 2:
self.regB = 33
regBassigned = True
if int(dut.io_bus_ar_valid) & int(dut.io_bus_ar_ready) == 1:
addr = int(dut.io_bus_ar_payload_addr)
self.readAddresses.put(addr)
if (int(dut.io_bus_aw_valid) & int(dut.io_bus_aw_ready)
& int(dut.io_bus_w_valid) & int(dut.io_bus_w_ready)) == 1:
addr = int(dut.io_bus_aw_payload_addr)
if addr == 9:
self.regA = truncUInt(
int(dut.io_bus_w_payload_data) >> 10, 20)
if addr == 7 and not regBassigned:
self.regB = truncUInt(
int(dut.io_bus_w_payload_data) >> 10, 20)
if addr == 15:
self.regA = 11
def spiSlaveAgent(spi, queue, clk):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
@coroutine
def wait(cycles):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
sclkLast = str(spi.sclk)
mosiLast = str(spi.mosi)
ssLast = str(spi.ss)
for i in xrange(cycles):
yield RisingEdge(clk)
sclkNew = str(spi.sclk)
mosiNew = str(spi.mosi)
ssNew = str(spi.ss)
sclkStable += 1
mosiStable += 1
ssStable += 1
if sclkNew != sclkLast:
sclkStableLast = sclkStable
sclkStable = 0
if mosiNew != mosiLast:
mosiStableLast = mosiStable
mosiStable = 0
if ssNew != ssLast:
ssStableLast = ssStable
ssStable = 0
sclkLast = sclkNew
mosiLast = mosiNew
ssLast = ssNew
ssValue = 0xF
while True:
if queue.empty():
yield wait(1)
# assert(sclkStable > 1)
# assert(mosiStable > 1)
# assert(ssStable > 1)
else:
head = queue.get()
if isinstance(head, SlaveCmdData):
for i in xrange(8):
if spiConfig.cpha == False:
spi.miso <= testBit(head.slaveData, 7-i) if head.slaveData != None else randBool()
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToogle
assert mosiStable >= spiConfig.sclkToogle
assertEquals(spi.mosi, testBit(head.masterData, 7-i),"MOSI missmatch")
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToogle
else:
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
spi.miso <= testBit(head.slaveData, 7 - i) if head.slaveData != None else randBool()
assert sclkStableLast >= spiConfig.sclkToogle
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert mosiStable >= spiConfig.sclkToogle
assert sclkStableLast >= spiConfig.sclkToogle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i), "MOSI missmatch")
elif isinstance(head, SlaveCmdSs):
while True:
yield wait(1)
assert sclkStable > 0
if spi.ss != ssValue:
break
if head.enable:
yield wait(spiConfig.ssSetup-1)
print str(ssStable) + " " + str(sclkStable)
assert ssStable >= spiConfig.ssSetup-1
assert sclkStable >= spiConfig.ssSetup-1
else:
print str(ssStableLast) + " " + str(sclkStable)
assert ssStableLast >= spiConfig.ssHold
assert sclkStable >= spiConfig.ssHold
yield wait(spiConfig.ssDisable-1)
print str(ssStable) + " " + str(sclkStable)
assert ssStable >= spiConfig.ssDisable-1
assert sclkStable >= spiConfig.ssDisable-1
assertEquals(spi.ss, setBit(ssValue, head.index, not head.enable), "SS mismatch")
ssValue = int(spi.ss)
def checkPin(value,cycles,pin,clk):
for i in range(0,cycles):
yield RisingEdge(clk)
assertEquals(value, pin, "io_uart_uart_txd")
def onOutput(self,payload,portId):
assertEquals(payload,self.queues[self.nextPort].get(),"ArbiterLowIdPortNoLockFirst payload error")
self.counter += 1
self.nextPort = -1
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
for i in range(0, 1000):
randSignal(dut.io_conds_0)
randSignal(dut.io_conds_1)
randSignal(dut.io_conds_2)
randSignal(dut.io_conds_3)
randSignal(dut.io_conds_4)
randSignal(dut.io_conds_5)
randSignal(dut.io_conds_6)
randSignal(dut.io_conds_7)
randSignal(dut.io_inAA_bod_gggg)
randSignal(dut.io_inAA_bod_aosi)
randSignal(dut.io_inAA_ahe)
randSignal(dut.io_inAA_zwg)
randSignal(dut.io_inAA_vsw)
randSignal(dut.io_inAA_lwee)
randSignal(dut.io_inAABits)
randSignal(dut.io_inUIntA)
randSignal(dut.io_inUIntB)
randSignal(dut.io_assign_sel_0)
randSignal(dut.io_assign_sel_1)
randSignal(dut.io_assign_sel_2)
randSignal(dut.io_assign_sel_3)
yield Timer(1000)
ref = Ref(dut)
assertEquals(ref.io_complexLiteral, dut.io_complexLiteral,
"io_complexLiteral")
assertEquals(ref.io_outAA_bod_gggg, dut.io_outAA_bod_gggg,
"io_outAA_bod_gggg")
assertEquals(ref.io_outAA_bod_aosi, dut.io_outAA_bod_aosi,
"io_outAA_bod_aosi")
assertEquals(ref.io_outAA_ahe, dut.io_outAA_ahe, "io_outAA_ahe")
assertEquals(ref.io_outAA_zwg, dut.io_outAA_zwg, "io_outAA_zwg")
assertEquals(ref.io_outAA_vsw, dut.io_outAA_vsw, "io_outAA_vsw")
assertEquals(ref.io_outAA_lwee, dut.io_outAA_lwee, "io_outAA_lwee")
assertEquals(ref.io_outAABits, dut.io_outAABits, "io_outAABits")
assertEquals(ref.io_outUIntAdder, dut.io_outUIntAdder,
"io_outUIntAdder")
assertEquals(ref.io_assign_bitDemux, dut.io_assign_bitDemux,
"io_assign_bitDemux")
dut.log.info("Cocotb test done")
def onOutput(self,payload,portId):
assertEquals(payload,self.queues[portId].get(),"fork error")
self.counters[portId] += 1
def jtagBridgeReadAssert(ctrl, address, size,value,mask = -1):
yield jtagBridgeCmd(ctrl, address,0, size, 0)
tab = [0,0]
yield jtagBridgeRsp(ctrl, tab)
assertEquals(tab[0], 1, "rsp not ready")
assertEquals(tab[1] & mask, value, "wrong rsp, expected" + str(value))
def jtagBridgeReadAssert(ctrl, address, size, value, mask=-1):
yield jtagBridgeCmd(ctrl, address, 0, size, 0)
tab = [0, 0]
yield jtagBridgeRsp(ctrl, tab)
assertEquals(tab[0], 1, "rsp not ready")
assertEquals(tab[1] & mask, value, "wrong rsp, expected" + str(value))
def onOutput(self, payload, portId):
assertEquals(payload, self.queues[portId].get(), "fork error")
self.counters[portId] += 1
def readCoreValueAssert(dut, value, message):
print(message)
rsp = yield readCoreValue(dut)
assertEquals(rsp, value, message)
def applyFallingEdge(self):
while True:
yield FallingEdge(self.dut.clkn)
assertEquals(self.dut.test_clkn_regWithoutReset, self.test_clkn_regWithoutReset, "test_clkn_regWithoutReset")
self.test_clkn_regWithoutReset = (self.test_clkn_regWithoutReset + 1) & 0xFF
def applyRisingEdge(self):
dut = self.dut
while True:
yield RisingEdge(dut.clk)
assertEquals(dut.test_clk_regWithoutReset, self.test_clk_regWithoutReset, "test_clk_regWithoutReset")
assertEquals(dut.test_clk_boot_regWithoutReset, self.test_clk_boot_regWithoutReset, "test_clk_boot_regWithoutReset")
assertEquals(dut.test_clk_boot_regWithReset, self.test_clk_boot_regWithReset, "test_clk_boot_regWithReset")
assertEquals(dut.test_async_reset_regWithoutReset, self.test_async_reset_regWithoutReset, "test_async_reset_regWithoutReset")
assertEquals(dut.test_async_reset_regWithReset, self.test_async_reset_regWithReset, "test_async_reset_regWithReset")
assertEquals(dut.test_async_resetn_regWithoutReset, self.test_async_resetn_regWithoutReset, "test_async_resetn_regWithoutReset")
assertEquals(dut.test_async_resetn_regWithReset, self.test_async_resetn_regWithReset, "test_async_resetn_regWithReset")
assertEquals(dut.test_sync_reset_regWithoutReset, self.test_sync_reset_regWithoutReset, "test_sync_reset_regWithoutReset")
assertEquals(dut.test_sync_reset_regWithReset, self.test_sync_reset_regWithReset, "test_sync_reset_regWithReset")
assertEquals(dut.test_sync_resetn_regWithoutReset, self.test_sync_resetn_regWithoutReset, "test_sync_resetn_regWithoutReset")
assertEquals(dut.test_sync_resetn_regWithReset, self.test_sync_resetn_regWithReset, "test_sync_resetn_regWithReset")
assertEquals(dut.test_enable_regWithoutReset, self.test_enable_regWithoutReset, "test_enable_regWithoutReset")
assertEquals(dut.test_enablen_regWithoutReset, self.test_enablen_regWithoutReset, "test_enablen_regWithoutReset")
assertEquals(dut.test_sync_reset_enable_regWithoutReset, self.test_sync_reset_enable_regWithoutReset, "test_sync_reset_enable_regWithoutReset")
assertEquals(dut.test_sync_reset_enable_regWithReset, self.test_sync_reset_enable_regWithReset, "test_sync_reset_enable_regWithReset")
assertEquals(dut.test_softReset_regWithoutReset, self.test_softReset_regWithoutReset, "test_softReset_regWithoutReset")
assertEquals(dut.test_softReset_regWithReset, self.test_softReset_regWithReset, "test_softReset_regWithReset")
assertEquals(dut.test_softResetn_regWithoutReset, self.test_softResetn_regWithoutReset, "test_softResetn_regWithoutReset")
assertEquals(dut.test_softResetn_regWithReset, self.test_softResetn_regWithReset, "test_softResetn_regWithReset")
assertEquals(dut.test_async_reset_softReset_regWithoutReset, self.test_async_reset_softReset_regWithoutReset, "test_async_reset_softReset_regWithoutReset")
assertEquals(dut.test_async_reset_softReset_regWithReset, self.test_async_reset_softReset_regWithReset, "test_async_reset_softReset_regWithReset")
assertEquals(dut.test_sync_reset_softReset_regWithoutReset, self.test_sync_reset_softReset_regWithoutReset, "test_sync_reset_softReset_regWithoutReset")
assertEquals(dut.test_sync_reset_softReset_regWithReset, self.test_sync_reset_softReset_regWithReset, "test_sync_reset_softReset_regWithReset")
self.test_clk_regWithoutReset = (self.test_clk_regWithoutReset + 1) & 0xFF
self.test_clk_boot_regWithoutReset = (self.test_clk_boot_regWithoutReset + 1) & 0xFF
self.test_clk_boot_regWithReset = (self.test_clk_boot_regWithReset + 1) & 0xFF
self.test_async_reset_regWithoutReset = (self.test_async_reset_regWithoutReset + 1) & 0xFF
if int(dut.asyncReset) == 0:
self.test_async_reset_regWithReset = (self.test_async_reset_regWithReset + 1) & 0xFF
self.test_async_resetn_regWithoutReset = (self.test_async_resetn_regWithoutReset + 1) & 0xFF
if int(dut.asyncResetn) == 1:
self.test_async_resetn_regWithReset = (self.test_async_resetn_regWithReset + 1) & 0xFF
self.test_sync_reset_regWithoutReset = (self.test_sync_reset_regWithoutReset + 1) & 0xFF
self.test_sync_resetn_regWithoutReset = (self.test_sync_resetn_regWithoutReset + 1) & 0xFF
if int(dut.syncReset) == 1:
self.test_sync_reset_regWithReset = 42
else:
self.test_sync_reset_regWithReset = (self.test_sync_reset_regWithReset + 1) & 0xFF
if int(dut.syncResetn) == 0:
self.test_sync_resetn_regWithReset = 42
else:
self.test_sync_resetn_regWithReset = (self.test_sync_resetn_regWithReset + 1) & 0xFF
if int(dut.enable) == 1:
self.test_enable_regWithoutReset = (self.test_enable_regWithoutReset + 1) & 0xFF
if int(dut.enablen) == 0:
self.test_enablen_regWithoutReset = (self.test_enablen_regWithoutReset + 1) & 0xFF
if int(dut.enable) == 1:
self.test_sync_reset_enable_regWithoutReset = (self.test_sync_reset_enable_regWithoutReset + 1) & 0xFF
if int(dut.enable) == 1:
if int(dut.syncReset) == 1:
self.test_sync_reset_enable_regWithReset = 42
else:
self.test_sync_reset_enable_regWithReset = (self.test_sync_reset_enable_regWithReset + 1) & 0xFF
self.test_softReset_regWithoutReset = (self.test_softReset_regWithoutReset + 1) & 0xFF
if int(dut.softReset) == 1:
self.test_softReset_regWithReset = 42
else:
self.test_softReset_regWithReset = (self.test_softReset_regWithReset + 1) & 0xFF
self.test_softResetn_regWithoutReset = (self.test_softResetn_regWithoutReset + 1) & 0xFF
if int(dut.softResetn) == 0:
self.test_softResetn_regWithReset = 42
else:
self.test_softResetn_regWithReset = (self.test_softResetn_regWithReset + 1) & 0xFF
self.test_async_reset_softReset_regWithoutReset = (self.test_async_reset_softReset_regWithoutReset + 1) & 0xFF
if int(dut.asyncReset) == 0:
if int(dut.softReset) == 1:
self.test_async_reset_softReset_regWithReset = 42
else:
self.test_async_reset_softReset_regWithReset = (self.test_async_reset_softReset_regWithReset + 1) & 0xFF
self.test_sync_reset_softReset_regWithoutReset = (self.test_sync_reset_softReset_regWithoutReset + 1) & 0xFF
if int(dut.softReset) == 1 or int(dut.syncReset) == 1:
self.test_sync_reset_softReset_regWithReset = 42
else:
self.test_sync_reset_softReset_regWithReset = (self.test_sync_reset_softReset_regWithReset + 1) & 0xFF
def onOutput(self, payload, portId):
assertEquals(payload, self.queues[self.nextPort].get(),
"ArbiterLowIdPortNoLockFirst payload error")
self.counter += 1
self.nextPort = -1
def checkPin(value,cycles,pin,clk):
for i in range(0,cycles):
yield RisingEdge(clk)
assertEquals(value, pin, "io_uart_uart_txd")
def onOutput(self,payload,portId):
assertEquals(payload,self.queues[self.nextPort].get(),"ArbiterInOrder payload error")
self.nextPort = (self.nextPort + 1) % 3
self.counter += 1
def readCoreValueAssert(dut,value,message):
print(message)
rsp = yield readCoreValue(dut)
assertEquals(rsp,value,message)
def applyRisingEdge(self):
dut = self.dut
while True:
yield RisingEdge(dut.clk)
assertEquals(dut.test_clk_regWithoutReset,
self.test_clk_regWithoutReset,
"test_clk_regWithoutReset")
assertEquals(dut.test_clk_boot_regWithoutReset,
self.test_clk_boot_regWithoutReset,
"test_clk_boot_regWithoutReset")
assertEquals(dut.test_clk_boot_regWithReset,
self.test_clk_boot_regWithReset,
"test_clk_boot_regWithReset")
assertEquals(dut.test_async_reset_regWithoutReset,
self.test_async_reset_regWithoutReset,
"test_async_reset_regWithoutReset")
assertEquals(dut.test_async_reset_regWithReset,
self.test_async_reset_regWithReset,
"test_async_reset_regWithReset")
assertEquals(dut.test_async_resetn_regWithoutReset,
self.test_async_resetn_regWithoutReset,
"test_async_resetn_regWithoutReset")
assertEquals(dut.test_async_resetn_regWithReset,
self.test_async_resetn_regWithReset,
"test_async_resetn_regWithReset")
assertEquals(dut.test_sync_reset_regWithoutReset,
self.test_sync_reset_regWithoutReset,
"test_sync_reset_regWithoutReset")
assertEquals(dut.test_sync_reset_regWithReset,
self.test_sync_reset_regWithReset,
"test_sync_reset_regWithReset")
assertEquals(dut.test_sync_resetn_regWithoutReset,
self.test_sync_resetn_regWithoutReset,
"test_sync_resetn_regWithoutReset")
assertEquals(dut.test_sync_resetn_regWithReset,
self.test_sync_resetn_regWithReset,
"test_sync_resetn_regWithReset")
assertEquals(dut.test_enable_regWithoutReset,
self.test_enable_regWithoutReset,
"test_enable_regWithoutReset")
assertEquals(dut.test_enablen_regWithoutReset,
self.test_enablen_regWithoutReset,
"test_enablen_regWithoutReset")
assertEquals(dut.test_sync_reset_enable_regWithoutReset,
self.test_sync_reset_enable_regWithoutReset,
"test_sync_reset_enable_regWithoutReset")
assertEquals(dut.test_sync_reset_enable_regWithReset,
self.test_sync_reset_enable_regWithReset,
"test_sync_reset_enable_regWithReset")
assertEquals(dut.test_softReset_regWithoutReset,
self.test_softReset_regWithoutReset,
"test_softReset_regWithoutReset")
assertEquals(dut.test_softReset_regWithReset,
self.test_softReset_regWithReset,
"test_softReset_regWithReset")
assertEquals(dut.test_softResetn_regWithoutReset,
self.test_softResetn_regWithoutReset,
"test_softResetn_regWithoutReset")
assertEquals(dut.test_softResetn_regWithReset,
self.test_softResetn_regWithReset,
"test_softResetn_regWithReset")
assertEquals(dut.test_async_reset_softReset_regWithoutReset,
self.test_async_reset_softReset_regWithoutReset,
"test_async_reset_softReset_regWithoutReset")
assertEquals(dut.test_async_reset_softReset_regWithReset,
self.test_async_reset_softReset_regWithReset,
"test_async_reset_softReset_regWithReset")
assertEquals(dut.test_sync_reset_softReset_regWithoutReset,
self.test_sync_reset_softReset_regWithoutReset,
"test_sync_reset_softReset_regWithoutReset")
assertEquals(dut.test_sync_reset_softReset_regWithReset,
self.test_sync_reset_softReset_regWithReset,
"test_sync_reset_softReset_regWithReset")
self.test_clk_regWithoutReset = (self.test_clk_regWithoutReset +
1) & 0xFF
self.test_clk_boot_regWithoutReset = (
self.test_clk_boot_regWithoutReset + 1) & 0xFF
self.test_clk_boot_regWithReset = (
self.test_clk_boot_regWithReset + 1) & 0xFF
self.test_async_reset_regWithoutReset = (
self.test_async_reset_regWithoutReset + 1) & 0xFF
if int(dut.asyncReset) == 0:
self.test_async_reset_regWithReset = (
self.test_async_reset_regWithReset + 1) & 0xFF
self.test_async_resetn_regWithoutReset = (
self.test_async_resetn_regWithoutReset + 1) & 0xFF
if int(dut.asyncResetn) == 1:
self.test_async_resetn_regWithReset = (
self.test_async_resetn_regWithReset + 1) & 0xFF
self.test_sync_reset_regWithoutReset = (
self.test_sync_reset_regWithoutReset + 1) & 0xFF
self.test_sync_resetn_regWithoutReset = (
self.test_sync_resetn_regWithoutReset + 1) & 0xFF
if int(dut.syncReset) == 1:
self.test_sync_reset_regWithReset = 42
else:
self.test_sync_reset_regWithReset = (
self.test_sync_reset_regWithReset + 1) & 0xFF
if int(dut.syncResetn) == 0:
self.test_sync_resetn_regWithReset = 42
else:
self.test_sync_resetn_regWithReset = (
self.test_sync_resetn_regWithReset + 1) & 0xFF
if int(dut.enable) == 1:
self.test_enable_regWithoutReset = (
self.test_enable_regWithoutReset + 1) & 0xFF
if int(dut.enablen) == 0:
self.test_enablen_regWithoutReset = (
self.test_enablen_regWithoutReset + 1) & 0xFF
if int(dut.enable) == 1:
self.test_sync_reset_enable_regWithoutReset = (
self.test_sync_reset_enable_regWithoutReset + 1) & 0xFF
if int(dut.enable) == 1:
if int(dut.syncReset) == 1:
self.test_sync_reset_enable_regWithReset = 42
else:
self.test_sync_reset_enable_regWithReset = (
self.test_sync_reset_enable_regWithReset + 1) & 0xFF
self.test_softReset_regWithoutReset = (
self.test_softReset_regWithoutReset + 1) & 0xFF
if int(dut.softReset) == 1:
self.test_softReset_regWithReset = 42
else:
self.test_softReset_regWithReset = (
self.test_softReset_regWithReset + 1) & 0xFF
self.test_softResetn_regWithoutReset = (
self.test_softResetn_regWithoutReset + 1) & 0xFF
if int(dut.softResetn) == 0:
self.test_softResetn_regWithReset = 42
else:
self.test_softResetn_regWithReset = (
self.test_softResetn_regWithReset + 1) & 0xFF
self.test_async_reset_softReset_regWithoutReset = (
self.test_async_reset_softReset_regWithoutReset + 1) & 0xFF
if int(dut.asyncReset) == 0:
if int(dut.softReset) == 1:
self.test_async_reset_softReset_regWithReset = 42
else:
self.test_async_reset_softReset_regWithReset = (
self.test_async_reset_softReset_regWithReset +
1) & 0xFF
self.test_sync_reset_softReset_regWithoutReset = (
self.test_sync_reset_softReset_regWithoutReset + 1) & 0xFF
if int(dut.softReset) == 1 or int(dut.syncReset) == 1:
self.test_sync_reset_softReset_regWithReset = 42
else:
self.test_sync_reset_softReset_regWithReset = (
self.test_sync_reset_softReset_regWithReset + 1) & 0xFF
def testMD5EngineStd(dut):
dut.log.info("Cocotb test MD5 Engine Std")
from cocotblib.misc import cocotbXHack
cocotbXHack()
helperMD5 = MD5EngineStdHelper(dut)
clockDomain = ClockDomain(helperMD5.io.clk, 200)
# Start clock
cocotb.fork(clockDomain.start())
# Init IO and wait the end of the reset
helperMD5.io.initIO()
#yield clockDomain.event_endReset.wait()
yield RisingEdge(helperMD5.io.clk)
# start monitoring rsp
helperMD5.io.rsp.startMonitoringValid(helperMD5.io.clk)
# Fix patterns
msgs = [
[
0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
],
[
0x00000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
],
[
0x80636261000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001800000000
],
[
0x34333231383736353231303936353433303938373433323138373635323130393635343330393837343332313837363532313039363534333039383734333231,
0x38373635323130393635343330393837000000800000000000000000000000000000000000000000000000000000000000000000000000000000028000000000
]
]
digests = [
0x031F1DAC6EA58ED01FAB67B774317791, 0xD98C1DD404B2008F980980E97E42F8EC,
0x98500190B04FD23C7D3F96D6727FE128, 0xA2F4ED5755C9E32B2EDA49AC7AB60721
]
# Process all pattern
indexPattern = 0
for msgPattern in msgs:
# Init MD5
yield RisingEdge(helperMD5.io.clk)
helperMD5.io.init <= 1
yield RisingEdge(helperMD5.io.clk)
helperMD5.io.init <= 0
yield RisingEdge(helperMD5.io.clk)
for msgBlock in msgPattern:
# Hash data
helperMD5.io.cmd.valid <= 1
helperMD5.io.cmd.payload.block <= msgBlock
# wait the end of the encryption
yield helperMD5.io.rsp.event_valid.wait()
helperMD5.io.cmd.valid <= 0
rtlDigest = "{0:0>4X}".format(
int(str(helperMD5.io.rsp.payload.digest), 2))
yield RisingEdge(helperMD5.io.clk)
assertEquals(int(rtlDigest, 16), digests[indexPattern], "Wrong digest")
yield RisingEdge(helperMD5.io.clk)
yield Timer(50000)
indexPattern += 1
def onOutput(self, payload, portId):
assertEquals(payload, self.queue.get(),
"DispatcherInOrder payload error")
assertEquals(portId, self.nextPort, "DispatcherInOrder order error")
self.nextPort = (self.nextPort + 1) % 3
self.counter += 1
def spiSlaveAgent(spi, queue, clk):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
@coroutine
def wait(cycles):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
sclkLast = str(spi.sclk)
mosiLast = str(spi.mosi)
ssLast = str(spi.ss)
for i in range(cycles):
yield RisingEdge(clk)
sclkNew = str(spi.sclk)
mosiNew = str(spi.mosi)
ssNew = str(spi.ss)
sclkStable += 1
mosiStable += 1
ssStable += 1
if sclkNew != sclkLast:
sclkStableLast = sclkStable
sclkStable = 0
if mosiNew != mosiLast:
mosiStableLast = mosiStable
mosiStable = 0
if ssNew != ssLast:
ssStableLast = ssStable
ssStable = 0
sclkLast = sclkNew
mosiLast = mosiNew
ssLast = ssNew
ssValue = 0xF
while True:
if queue.empty():
yield wait(1)
# assert(sclkStable > 1)
# assert(mosiStable > 1)
# assert(ssStable > 1)
else:
head = queue.get()
if isinstance(head, SlaveCmdData):
for i in range(8):
if spiConfig.cpha == False:
spi.miso <= testBit(
head.slaveData, 7 -
i) if head.slaveData != None else randBool()
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToggle
assert mosiStable >= spiConfig.sclkToggle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i),
"MOSI mismatch")
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToggle
else:
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
spi.miso <= testBit(
head.slaveData, 7 -
i) if head.slaveData != None else randBool()
assert sclkStableLast >= spiConfig.sclkToggle
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert mosiStable >= spiConfig.sclkToggle
assert sclkStableLast >= spiConfig.sclkToggle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i),
"MOSI mismatch")
elif isinstance(head, SlaveCmdSs):
while True:
yield wait(1)
assert sclkStable > 0
if spi.ss != ssValue:
break
if head.enable:
yield wait(spiConfig.ssSetup - 1)
print(str(ssStable) + " " + str(sclkStable))
assert ssStable >= spiConfig.ssSetup - 1
assert sclkStable >= spiConfig.ssSetup - 1
else:
print(str(ssStableLast) + " " + str(sclkStable))
assert ssStableLast >= spiConfig.ssHold
assert sclkStable >= spiConfig.ssHold
yield wait(spiConfig.ssDisable - 1)
print(str(ssStable) + " " + str(sclkStable))
assert ssStable >= spiConfig.ssDisable - 1
assert sclkStable >= spiConfig.ssDisable - 1
assertEquals(spi.ss,
setBit(ssValue, head.index, not head.enable),
"SS mismatch")
ssValue = int(spi.ss)
def onOutput(self,payload,portId):
assertEquals(payload,self.queue.get(),"DispatcherInOrder payload error")
assertEquals(portId,self.nextPort,"DispatcherInOrder order error")
self.nextPort = (self.nextPort + 1) % 3
self.counter += 1
def testDESCore(dut):
dut.log.info("Cocotb test DES Core")
from cocotblib.misc import cocotbXHack
cocotbXHack()
helperDES = DESCoreStdHelper(dut)
clockDomain = ClockDomain(helperDES.io.clk, 200, helperDES.io.resetn,
RESET_ACTIVE_LEVEL.LOW)
# Start clock
cocotb.fork(clockDomain.start())
# Init IO and wait the end of the reset
helperDES.io.init()
yield clockDomain.event_endReset.wait()
# start monitoring the Valid signal
helperDES.io.rsp.startMonitoringValid(helperDES.io.clk)
for _ in range(0, 5):
# Vector test ...
#key = 0xAABB09182736CCDD
#data = 0x123456ABCD132536
#data = 0xC0B7A8D05F3A829C
# Gen random value
key = randBits(64)
data = randBits(64)
# Encrpytion
helperDES.io.cmd.valid <= 1
helperDES.io.cmd.payload.key <= key
helperDES.io.cmd.payload.block <= data
helperDES.io.cmd.payload.enc <= 1 # do an encryption
# Wait the end of the process and read the result
yield helperDES.io.rsp.event_valid.wait()
rtlEncryptedBlock = int(helperDES.io.rsp.event_valid.data.block)
#print("RTL encrypted", hex(rtlEncryptedBlock))
helperDES.io.cmd.valid <= 0
yield RisingEdge(helperDES.io.clk)
# Encrpytion
helperDES.io.cmd.valid <= 1
helperDES.io.cmd.payload.key <= key
helperDES.io.cmd.payload.block <= rtlEncryptedBlock
helperDES.io.cmd.payload.enc <= 0 # do a decryption
# Wait the end of the process and read the result
yield helperDES.io.rsp.event_valid.wait()
rtlDecryptedBlock = int(helperDES.io.rsp.event_valid.data.block)
#print("RTL decrypted", hex(rtlDecryptedBlock))
helperDES.io.cmd.valid <= 0
yield RisingEdge(helperDES.io.clk)
# Encrypted data with the model
k = des(int_2_String(key),
CBC,
"\0\0\0\0\0\0\0\0",
pad=None,
padmode=PAD_PKCS5)
refEncryptedOutput = (k.encrypt(int_2_String(data))).encode('hex')[:16]
# print("Ref encrypted ", refEncryptedOutput)
# compare result
assertEquals(int(refEncryptedOutput, 16), rtlEncryptedBlock,
"Encryption data wrong ")
assertEquals(rtlDecryptedBlock, data, "Decryption data wrong ")
dut.log.info("Cocotb end test DES Core")
def test1(dut):
random.seed(0)
outputs = [Bundle(dut, "io_outputs_" + str(i)) for i in range(4)]
mappings = [[0x0000, 0x1000], [0x1000, 0x1000], [0x4000, 0x2000],
[0x6000, 0x3000]]
for i in range(100):
dut.io_input_PADDR <= randBits(16)
dut.io_input_PSEL <= randBits(1)
dut.io_input_PENABLE <= randBits(1)
dut.io_input_PWRITE <= randBits(1)
dut.io_input_PWDATA <= randBits(32)
for output in outputs:
output.PREADY <= randBits(1)
output.PRDATA <= randBits(32)
output.PSLVERROR <= randBits(1)
yield Timer(1000)
select = None
for index, mapping in enumerate(mappings):
if (int(dut.io_input_PADDR) >= mapping[0]
and int(dut.io_input_PADDR) < mapping[0] + mapping[1]):
select = index
for index, output in enumerate(outputs):
assertEquals(output.PADDR, dut.io_input_PADDR,
"fail on output PADDR " + str(index))
assertEquals(output.PWRITE, dut.io_input_PWRITE,
"fail on output PWRITE " + str(index))
if select == index:
assertEquals(output.PENABLE, dut.io_input_PENABLE,
"fail on output PENABLE " + str(index))
assertEquals(output.PSEL, dut.io_input_PSEL,
"fail on output PSEL " + str(index))
else:
assertEquals(output.PSEL, 0,
"fail on output PSEL " + str(index))
if select == index:
assertEquals(output.PREADY, dut.io_input_PREADY,
"fail on input PREADY")
assertEquals(output.PRDATA, dut.io_input_PRDATA,
"fail on input PRDATA")
assertEquals(output.PSLVERROR, dut.io_input_PSLVERROR,
"fail on input PSLVERROR")
def test1(dut):
dut.log.info("Cocotb test boot")
#random.seed(0)
dut.address <= 0
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,0,"1")
assertEquals(dut.data_uint,0,"1")
assertEquals(dut.data_sint,0,"1")
assertEquals(dut.data_enumeration,0,"1")
dut.address <= 1
yield Timer(10)
assertEquals(dut.data_bool,1,"1")
assertEquals(dut.data_bits,0,"1")
assertEquals(dut.data_uint,0,"1")
assertEquals(dut.data_sint,0,"1")
assertEquals(dut.data_enumeration,0,"1")
dut.address <= 2
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,511,"1")
assertEquals(dut.data_uint,0,"1")
assertEquals(dut.data_sint,0,"1")
assertEquals(dut.data_enumeration,0,"1")
dut.address <= 3
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,0,"1")
assertEquals(dut.data_uint,1023,"1")
assertEquals(dut.data_sint,0,"1")
assertEquals(dut.data_enumeration,0,"1")
dut.address <= 4
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,0,"1")
assertEquals(dut.data_uint,0,"1")
assertEquals(dut.data_sint,2047,"1")
assertEquals(dut.data_enumeration,0,"1")
dut.address <= 5
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,0,"1")
assertEquals(dut.data_uint,0,"1")
assertEquals(dut.data_sint,0,"1")
assertEquals(dut.data_enumeration,2,"1")
dut.address <= 6
yield Timer(10)
assertEquals(dut.data_bool,0,"1")
assertEquals(dut.data_bits,43,"1")
assertEquals(dut.data_uint,74,"1")
assertEquals(dut.data_sint,88,"1")
assertEquals(dut.data_enumeration,1,"1")
dut.log.info("Cocotb test done")
def onOutput(self, payload, portId):
assertEquals(payload, self.queues[self.nextPort].get(),
"ArbiterInOrder payload error")
self.nextPort = (self.nextPort + 1) % 3
self.counter += 1