def set_156_to_188(maroc3_id,value):
if value=="undef":
return 1,"ok"
retcode,res = common_roc.load_str(value,33,True)
if retcode==0:
return 0,"Error reading value to be applied: %s"%(res)
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.apply_mask,"set 156 to 188 bits",156,res)
def set_hg_tau(easiroc_id, hg_tau):
hg_tau = int(hg_tau)
if (hg_tau % 25) == 0 and hg_tau >= 0 and hg_tau <= 175:
hg_tau = hg_tau / 25
return common_roc.apply_to_roc(
easiroc_pool, easiroc_id, common_roc.apply_inv_mask, "set hg tau", 71, common_roc.split_bin(hg_tau, 3)
)
return 0, "high-gain time constant must be a multiple of 25ns between 0 and 175ns"
def set_lg_tau(easiroc_id, lg_tau):
lg_tau = int(lg_tau)
if (lg_tau % 25) == 0 and lg_tau >= 0 and lg_tau <= 175:
lg_tau = lg_tau / 25
return common_roc.apply_to_roc(
easiroc_pool, easiroc_id, common_roc.apply_inv_mask, "set lg tau", 76, common_roc.split_bin(lg_tau, 3)
)
return 0, "low-gain time constant must be a multiple of 25ns between 0 and 175ns"
def set_lg_fb_capa(easiroc_id, lg_fb_capa):
lg_fb_capa = float(lg_fb_capa)
if (lg_fb_capa % 0.1) == 0 and lg_fb_capa >= 0.1 and lg_fb_capa <= 1.5:
lg_fb_capa = int(15 - 10 * lg_fb_capa)
return common_roc.apply_to_roc(
easiroc_pool, easiroc_id, common_roc.apply_inv_mask, 149, common_roc.split_bin(lg_fb_capa, 4)
)
return 0, "low-gain preamp feedback capacitance must be a multiple of 0.1pF between 0.1pF and 1.5pF"
def set_chipid(skiroc_id,skiroc):
"set the chipid of a skiroc chip on its bitstream"
idbin=common_roc.split_bin(common_roc.bin2gray(int(skiroc["chipid"])),8)
retcode,res=common_roc.apply_to_roc(skiroc_pool,skiroc_id,common_roc.apply_mask,"set chipid",10,idbin)
if retcode==0:
return 0,res
retcode,res=submod.execcmd("set_param_cmod",skiroc_id,"skiroc_chipid",skiroc["chipid"])
if retcode==0:
return 0,res
return 1,"ok"
def set_lg_preamp_bias(easiroc_id, value):
if value == "undef":
return 1, "ok"
if value == "high":
value = "0"
elif value == "weak":
value = "1"
else:
return 0, "invalid state of lg preamp bias (high/weak): %s" % (value)
return common_roc.apply_to_roc(
easiroc_pool, easiroc_id, common_roc.apply_mask, "set state of lg preamp bias", 165, value
)
def set_hg_fb_capa(easiroc_id, hg_fb_capa):
hg_fb_capa = float(hg_fb_capa)
if (hg_fb_capa % 0.1) == 0 and hg_fb_capa >= 0.1 and hg_fb_capa <= 1.5:
hg_fb_capa = int(15 - 10 * hg_fb_capa)
return common_roc.apply_to_roc(
easiroc_pool,
easiroc_id,
common_roc.apply_mask,
153,
"set hg feedback capa",
common_roc.split_bin(hg_fb_capa, 4),
)
return 0, "high-gain preamp feedback capacitance must be a multiple of 0.1pF between 0.1pF and 1.5pF"
def set_lg_comp_capa(easiroc_id, lg_comp_capa):
lg_comp_capa = float(lg_comp_capa)
if (lg_comp_capa % 0.5) == 0 and lg_comp_capa >= 0 and lg_comp_capa <= 7:
lg_comp_capa = int(2 * lg_comp_capa)
return common_roc.apply_to_roc(
easiroc_pool,
easiroc_id,
common_roc.apply_inv_mask,
145,
"set lg comp capa",
common_roc.split_bin(lg_comp_capa, 4),
)
return 0, "low-gain preamp compensation capacitance must be a multiple of 0.5pF between 0pF and 7pF"
def set_hg_comp_capa(easiroc_id, hg_comp_capa):
hg_comp_capa = float(hg_comp_capa)
if (hg_comp_capa % 0.5) == 0 and hg_comp_capa >= 0 and hg_comp_capa <= 7:
hg_comp_capa = int(2 * hg_comp_capa)
return common_roc.apply_to_roc(
easiroc_pool,
easiroc_id,
common_roc.apply_mask,
157,
"set hg comp capa",
common_roc.split_bin(hg_comp_capa, 4),
)
return 0, "high-gain preamp compensation capacitance must be a multiple of 0.5pF between 0 and 7"
def set_trigmode(skiroc_id,mode):
"set the trigger mode of a skiroc"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_trigmode_reg,"set trigger mode",mode)
def set_dac1(maroc3_id,value):
if value!="undef":
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.apply_mask,"set DAC1 value",3,common_roc.split_bin(int(value),10))
return 1,"ok"
def set_pp_dacs(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"enable/disable power pulsing for all DACs",1,value)
def set_inv_start_counter_wlk(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"set start counter polarity switching",24,value)
def set_dac_code(easiroc_id, dac_code):
if dac_code != "undef":
return common_roc.apply_to_roc(
easiroc_pool, easiroc_id, common_roc.apply_mask, "set DAC code", 20, common_roc.split_bin(int(dac_code), 10)
)
return 1, "ok"
def set_d_output(easiroc_id, value):
return common_roc.apply_to_roc(easiroc_pool, easiroc_id, common_roc.on_off_bit, "enable/disable d output", 6, value)
def set_gtrigger(skiroc_id,gtrigger):
"set the trigger threshold of a skiroc"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_gtrigger_reg,"set trigger threshold",gtrigger)
def set_delay(skiroc_id,delay):
"set the hold delay of a skiroc"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_delay_reg,"set hold delay",delay)
def set_gtrigger(spiroc_id,gtrigger):
"set the trigger threshold of a spiroc"
if gtrigger!="undef":
return common_roc.apply_to_roc(spiroc_pool,spiroc_id,common_roc.apply_inv_mask,"set trigger threshold",239,common_roc.split_bin(int(gtrigger),10))
return 1,"ok"
def set_10bit_ramp_wlk(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"set 10bit ramp slope",26,value)
def set_cpcap(skiroc_id,cpcap):
"set the compensation capacitance of a skiroc"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_cpcap_reg,"set feedback capacitance",cpcap)
def set_pp_bandgap(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"enable/disable power pulsing for bandgap",0,value)
def set_fbcap(skiroc_id,fbcap):
"set the feedback capacitance of a skiroc"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_fbcap_reg,"set feedback capacitance",fbcap)
def set_small_dac(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"decrease/keep slope of DAC0",2,value)
def set_start_ro(skiroc_id,start_ro):
"start the readout set"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_start_ro_reg,"start the readout set",start_ro)
def set_data_output_wlk(maroc3_id,value):
return common_roc.apply_to_roc(maroc3_pool,maroc3_id,common_roc.on_off_bit,"set ADC data output",23,value)
def set_end_ro(skiroc_id,end_ro):
"end the readout set"
return common_roc.apply_to_roc(skiroc_pool,skiroc_id,set_end_ro_reg,"end the readout set",end_ro)
