def __setattr__(self, attr, value):
try:
object.__getattribute__(self, "init_done")
if attr in self.circuit.interface.ports.keys():
wrapper = PortWrapper(self.circuit.interface.ports[attr], self)
select_path = wrapper.select_path
select_path.tester.poke(select_path, value)
elif attr in self.instance_map and \
"reg_P" in type(self.instance_map[attr]).name:
try:
# Support directly poking coreir reg
wrapper = PortWrapper(
fault.WrappedVerilogInternalPort(
"outReg", self.instance_map[attr].O),
InstanceWrapper(self.instance_map[attr], self))
select_path = wrapper.select_path
select_path.tester.poke(select_path, value)
except Exception as e:
print(e)
exit(1)
else:
raise Exception(f"Could not set attr {attr} with value"
f" {value}")
except AttributeError:
object.__setattr__(self, attr, value)
def test_tester_verilog_wrapped(target, simulator):
SimpleALU = m.DefineFromVerilogFile("tests/simple_alu.v",
type_map={"CLK": m.In(m.Clock)},
target_modules=["SimpleALU"])[0]
circ = m.DefineCircuit("top",
"a", m.In(m.Bits[16]),
"b", m.In(m.Bits[16]),
"c", m.Out(m.Bits[16]),
"config_data", m.In(m.Bits[2]),
"config_en", m.In(m.Bit),
"CLK", m.In(m.Clock))
simple_alu = SimpleALU()
m.wire(simple_alu.a, circ.a)
m.wire(simple_alu.b, circ.b)
m.wire(simple_alu.c, circ.c)
m.wire(simple_alu.config_data, circ.config_data)
m.wire(simple_alu.config_en, circ.config_en)
m.wire(simple_alu.CLK, circ.CLK)
m.EndDefine()
tester = fault.Tester(circ, circ.CLK)
tester.verilator_include("SimpleALU")
tester.verilator_include("ConfigReg")
tester.circuit.CLK = 0
for i in range(0, 4):
tester.poke(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]),
i)
tester.step(2)
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]),
i)
signal = tester.peek(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]),
signal)
tester.expect(
fault.WrappedVerilogInternalPort(
"SimpleALU_inst0.config_reg.Q", m.Bits[2]),
i)
signal = tester.peek(
fault.WrappedVerilogInternalPort(
"SimpleALU_inst0.config_reg.Q", m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort(
"SimpleALU_inst0.config_reg.Q", m.Bits[2]),
signal)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_verilog_wrapped(target, simulator):
ConfigReg, SimpleALU = m.define_from_verilog_file(
"tests/simple_alu.v",
type_map={"CLK": m.In(m.Clock)},
target_modules=["SimpleALU", "ConfigReg"])
with SimpleALU.open():
ConfigReg()
class circ(m.Circuit):
name = 'top'
io = m.IO(a=m.In(m.Bits[16]),
b=m.In(m.Bits[16]),
c=m.Out(m.Bits[16]),
config_data=m.In(m.Bits[2]),
config_en=m.In(m.Bit),
CLK=m.In(m.Clock))
simple_alu = SimpleALU()
simple_alu.a @= io.a
simple_alu.b @= io.b
io.c @= simple_alu.c
simple_alu.config_data @= io.config_data
simple_alu.config_en @= io.config_en
simple_alu.CLK @= io.CLK
tester = fault.Tester(circ, circ.CLK)
tester.verilator_include("SimpleALU")
tester.verilator_include("ConfigReg")
tester.circuit.CLK = 0
for i in range(0, 4):
tester.poke(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), i)
tester.step(2)
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]), i)
signal = tester.peek(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]), signal)
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), i)
signal = tester.peek(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), signal)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)