Esempio n. 1
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def get_build_env(kind, target_clk_ns):
    """Get board-related build environment for testing.
    - kind = either zynq or alveo.
    """
    ret = {}
    if kind == "zynq":
        ret["board"] = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
        ret["part"] = pynq_part_map[ret["board"]]
        ret["ip"] = os.getenv("PYNQ_IP", "")
        ret["username"] = os.getenv("PYNQ_USERNAME", "xilinx")
        ret["password"] = os.getenv("PYNQ_PASSWORD", "xilinx")
        ret["port"] = os.getenv("PYNQ_PORT", 22)
        ret["target_dir"] = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
        ret["build_fxn"] = ZynqBuild(ret["board"], target_clk_ns)
    elif kind == "alveo":
        ret["board"] = os.getenv("ALVEO_BOARD", default="U250")
        ret["part"] = alveo_part_map[ret["board"]]
        ret["platform"] = alveo_default_platform[ret["board"]]
        ret["ip"] = os.getenv("ALVEO_IP", "")
        ret["username"] = os.getenv("ALVEO_USERNAME", "")
        ret["password"] = os.getenv("ALVEO_PASSWORD", "")
        ret["port"] = os.getenv("ALVEO_PORT", 22)
        ret["target_dir"] = os.getenv("ALVEO_TARGET_DIR", "/tmp/finn_alveo_deploy")
        ret["build_fxn"] = VitisBuild(
            ret["part"],
            target_clk_ns,
            ret["platform"],
            strategy=VitisOptStrategy.BUILD_SPEED,
        )
    else:
        raise Exception("Unknown test build environment spec")
    return ret
Esempio n. 2
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def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
    """Synthesize a bitfile for the using the specified shell flow, using either
    Vivado or Vitis, to target the specified board."""

    if DataflowOutputType.BITFILE in cfg.generate_outputs:
        bitfile_dir = cfg.output_dir + "/bitfile"
        os.makedirs(bitfile_dir, exist_ok=True)
        report_dir = cfg.output_dir + "/report"
        os.makedirs(report_dir, exist_ok=True)
        partition_model_dir = cfg.output_dir + "/intermediate_models/kernel_partitions"
        if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
            model = model.transform(
                ZynqBuild(
                    cfg.board,
                    cfg.synth_clk_period_ns,
                    cfg.enable_hw_debug,
                    partition_model_dir=partition_model_dir,
                )
            )
            copy(model.get_metadata_prop("bitfile"), bitfile_dir + "/finn-accel.bit")
            copy(model.get_metadata_prop("hw_handoff"), bitfile_dir + "/finn-accel.hwh")
            copy(
                model.get_metadata_prop("vivado_synth_rpt"),
                report_dir + "/post_synth_resources.xml",
            )
            vivado_pynq_proj_dir = model.get_metadata_prop("vivado_pynq_proj")
            timing_rpt = (
                "%s/finn_zynq_link.runs/impl_1/top_wrapper_timing_summary_routed.rpt"
                % vivado_pynq_proj_dir
            )
            copy(timing_rpt, report_dir + "/post_route_timing.rpt")

        elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
            model = model.transform(
                VitisBuild(
                    cfg._resolve_fpga_part(),
                    cfg.synth_clk_period_ns,
                    cfg.vitis_platform,
                    strategy=cfg._resolve_vitis_opt_strategy(),
                    enable_debug=cfg.enable_hw_debug,
                    floorplan_file=cfg.vitis_floorplan_file,
                    partition_model_dir=partition_model_dir,
                )
            )
            copy(model.get_metadata_prop("bitfile"), bitfile_dir + "/finn-accel.xclbin")
            copy(
                model.get_metadata_prop("vivado_synth_rpt"),
                report_dir + "/post_synth_resources.xml",
            )
        else:
            raise Exception("Unrecognized shell_flow_type: " + str(cfg.shell_flow_type))
        print("Bitfile written into " + bitfile_dir)

    return model
Esempio n. 3
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def test_end2end_mobilenet_build():
    model = load_test_checkpoint_or_skip(build_dir +
                                         "/end2end_mobilenet_fifodepth.onnx")
    model = model.transform(
        VitisBuild(
            test_fpga_part,
            target_clk_ns,
            test_platform,
            strategy=VitisOptStrategy.PERFORMANCE_BEST,
        ))
    model.save(build_dir + "/end2end_mobilenet_build.onnx")
    model = model.transform(AnnotateResources("synth"))
    model.save(build_dir + "/end2end_mobilenet_final.onnx")
Esempio n. 4
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def test_fpgadataflow_ipstitch_vitis(board, period_ns, extw):
    if "VITIS_PATH" not in os.environ:
        pytest.skip("VITIS_PATH not set")
    platform = alveo_default_platform[board]
    fpga_part = alveo_part_map[board]
    model = create_two_fc_model("external" if extw else "decoupled")
    if model.graph.node[0].op_type == "StreamingDataflowPartition":
        sdp_node = getCustomOp(model.graph.node[0])
        assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
        assert os.path.isfile(sdp_node.get_nodeattr("model"))
        model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
    model = model.transform(VitisBuild(fpga_part, period_ns, platform))
    model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_vitis.onnx")
    assert model.get_metadata_prop("platform") == "alveo"
    assert os.path.isdir(model.get_metadata_prop("vitis_link_proj"))
    assert os.path.isfile(model.get_metadata_prop("bitfile"))