def print_fpu_regs(cpu, f, x, i, b):
if f + x + i + b == 0:
x = 1
if f + x + i + b > 1:
print "Only one flag of -f, -x, -i, -b can be given to the command"
return
pr("Double precision (64-bit), ")
fp_regs = cpu.fprs[None]
prec = "d"
mult = 1
fdigits = 15
fsize = 23
if f:
pr("floating point view\n")
if x:
pr("hexadecimal integer view\n")
if i:
pr("decimal integer view\n")
if b:
pr("binary floating point view\n")
for c in range(len(fp_regs)):
pr("%%f%-2d " % (c * mult))
if f:
pr("%s\n" % fp_to_string.fp_to_string_fixed(
prec, fp_regs[c], fdigits, fsize))
if x:
pr("0x%x\n" % fp_regs[c])
if i:
pr("%d\n" % fp_regs[c])
if b:
pr("%s\n" % fp_to_string.fp_to_binstring(prec, fp_regs[c]))
pr("\n")
# Floating point status and control register (optional)
fpscr = SIM_read_register(cpu, SIM_get_register_number(cpu, "fpscr"))
round_kind = ["round-nearest", "round-zero", "round-pinf", "round-ninf"]
fpscr_64bit_targets = ['ppc-power6']
if cpu.classname in fpscr_64bit_targets:
fpscr_field_length = 16
else:
fpscr_field_length = 8
pr("fpscr = 0x%.*x " % (fpscr_field_length, fpscr))
pr("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s %s\n" %
(iff(fpscr & 0x80000000, "FX ", ""), iff(
fpscr & 0x40000000, "FEX ", ""), iff(fpscr & 0x20000000, "VX ", ""),
iff(fpscr & 0x10000000, "OX ", ""), iff(fpscr & 0x08000000, "UX ", ""),
iff(fpscr & 0x04000000, "ZX ", ""), iff(fpscr & 0x02000000, "XX ", ""),
iff(fpscr & 0x01000000, "VXSNAN ",
""), iff(fpscr & 0x00800000, "VXISI ",
""), iff(fpscr & 0x00400000, "VXIDI ",
""), iff(fpscr & 0x00200000, "VXZDZ ", ""),
iff(fpscr & 0x00100000, "VXIMZ ", ""),
iff(fpscr & 0x00080000, "VXVC ", ""), iff(
fpscr & 0x00040000, "FR ", ""), iff(fpscr & 0x00020000, "FI ", ""),
("FPRF[%s%s%s%s%s] " %
(iff(fpscr & 0x00010000, "C", ""), iff(fpscr & 0x00008000, "<", ""),
iff(fpscr & 0x00004000, ">", ""), iff(
fpscr & 0x00002000, "=", ""), iff(fpscr & 0x00001000, "?", ""))),
iff(fpscr & 0x00000400, "VXSOFT ",
""), iff(fpscr & 0x00000200, "VXSQRT ",
""), iff(fpscr & 0x00000100, "VXCVI ", ""),
iff(fpscr & 0x00000080, "VE ", ""), iff(fpscr & 0x00000040, "OE ", ""),
iff(fpscr & 0x00000020, "UE ", ""), iff(fpscr & 0x00000010, "ZE ", ""),
iff(fpscr & 0x00000008, "XE ", ""), iff(fpscr & 0x00000004, "NI ",
""), round_kind[fpscr & 3]))
def pregs_fpu_cmd(obj, s, d, q, f, x, i, b):
if f + x + i + b == 0:
x = 1
if s + d + q == 0:
d = 1
if f + x + i + b > 1:
print "Only one flag of -f, -x, -i, -b can be given to the command"
return
if s + d + q > 1:
print "Only one flag of -s, -d, -q can be given to the command"
return
if s:
pr("Single precision (32-bit), ")
tmp_fp_regs = obj.fp_registers[:16]
fp_regs = []
for c in range(16):
fp_regs.append((tmp_fp_regs[c] >> 32L) & 0xFFFFFFFFL)
fp_regs.append(tmp_fp_regs[c] & 0xFFFFFFFFL)
prec = "s"
mult = 1
fdigits = 8
fsize = 16
if d:
pr("Double precision (64-bit), ")
fp_regs = obj.fp_registers
prec = "d"
mult = 2
fdigits = 15
fsize = 23
if q:
pr("Quad precision (128-bit), ")
tmp_fp_regs = obj.fp_registers
fp_regs = []
for c in range(0,32,2):
fp_regs.append((tmp_fp_regs[c] << 64L) | (tmp_fp_regs[c+1]))
prec = "q"
mult = 4
fdigits = 22
fsize = 30
if f:
pr("floating point view\n")
if x:
pr("hexadecimal integer view\n")
if i:
pr("decimal integer view\n")
if b:
pr("binary floating point view\n")
for c in range(len(fp_regs)):
pr("%%f%-2d " % (c * mult))
if f:
pr("%s\n" % fp_to_string.fp_to_string_fixed(prec, fp_regs[c], fdigits, fsize))
if x:
pr("0x%x\n" % fp_regs[c])
if i:
pr("%d\n" % fp_regs[c])
if b:
pr("%s\n" % fp_to_string.fp_to_binstring(prec, fp_regs[c]))
fsr = sparc_read_int_register(obj, "fsr")
pr("\n")
pr(" RD NVM OFM UFM DZM NXM NS ftt nva ofa ufa dza nxa nvc ofc ufc dzc nxc\n")
rnd_str = ("near", "zero", "+inf", "-inf")
ftt_str = ("none ", "ieee ", "unfin", "unimp", "seq ", "hwerr", "nvreg")
pr("%%fsr = %s %d %d %d %d %d %d %s %d %d %d %d %d %d %d %d %d %d\n" %
(rnd_str[(fsr >> 30 & 3)],
(fsr >> 27) & 1,
(fsr >> 26) & 1,
(fsr >> 25) & 1,
(fsr >> 24) & 1,
(fsr >> 23) & 1,
(fsr >> 22) & 1,
ftt_str[(fsr >> 14) & 7],
(fsr >> 9) & 1,
(fsr >> 8) & 1,
(fsr >> 7) & 1,
(fsr >> 6) & 1,
(fsr >> 5) & 1,
(fsr >> 4) & 1,
(fsr >> 3) & 1,
(fsr >> 2) & 1,
(fsr >> 1) & 1,
(fsr >> 0) & 1))
if f + x + i + b > 1:
print "Only one flag of -f, -x, -i, -b can be given to the command"
return
if s + d > 1:
print "Only one flag of -s and -d can be given to the command"
return
for reg in xmm_regs:
pr("xmm%2d = " % iter)
if d:
sub = (reg[1], reg[0])
else:
sub = ((reg[1] >> 32) & 0xffffffffL, reg[1] & 0xffffffffL, (reg[0] >> 32) & 0xffffffffL, reg[0] & 0xffffffffL)
for r in sub:
if f:
if d:
pr(fp_to_string.fp_to_string_fixed("d", r, 15, 23) + " ")
else:
pr(fp_to_string.fp_to_string_fixed("s", r, 8, 16) + " ")
elif x:
if d:
pr("%016x " % r)
else:
pr("%08x " % r)
elif i:
if d:
pr("%20d " % r)
else:
pr("%10d " % r)
elif b:
if d:
pr(fp_to_string.fp_to_binstring("d", r))
print "Only one flag of -f, -x, -i, -b can be given to the command"
return
if s + d > 1:
print "Only one flag of -s and -d can be given to the command"
return
for reg in xmm_regs:
pr("xmm%2d = " % iter)
if d:
sub = (reg[1], reg[0])
else:
sub = ((reg[1] >> 32) & 0xffffffffL, reg[1] & 0xffffffffL,
(reg[0] >> 32) & 0xffffffffL, reg[0] & 0xffffffffL)
for r in sub:
if f:
if d:
pr(fp_to_string.fp_to_string_fixed("d", r, 15, 23) + " ")
else:
pr(fp_to_string.fp_to_string_fixed("s", r, 8, 16) + " ")
elif x:
if d:
pr("%016x " % r)
else:
pr("%08x " % r)
elif i:
if d:
pr("%20d " % r)
else:
pr("%10d " % r)
elif b:
if d:
pr(fp_to_string.fp_to_binstring("d", r))
def print_fpu_regs(cpu, f, x, i, b):
if f + x + i + b == 0:
x = 1
if f + x + i + b > 1:
print "Only one flag of -f, -x, -i, -b can be given to the command"
return
pr("Double precision (64-bit), ")
fp_regs = cpu.fprs[None]
prec = "d"
mult = 1
fdigits = 15
fsize = 23
if f:
pr("floating point view\n")
if x:
pr("hexadecimal integer view\n")
if i:
pr("decimal integer view\n")
if b:
pr("binary floating point view\n")
for c in range(len(fp_regs)):
pr("%%f%-2d " % (c * mult))
if f:
pr("%s\n" % fp_to_string.fp_to_string_fixed(prec, fp_regs[c], fdigits, fsize))
if x:
pr("0x%x\n" % fp_regs[c])
if i:
pr("%d\n" % fp_regs[c])
if b:
pr("%s\n" % fp_to_string.fp_to_binstring(prec, fp_regs[c]))
pr("\n")
# Floating point status and control register (optional)
fpscr = SIM_read_register(cpu, SIM_get_register_number(cpu, "fpscr"));
round_kind = [ "round-nearest", "round-zero", "round-pinf", "round-ninf" ];
fpscr_64bit_targets = ['ppc-power6']
if cpu.classname in fpscr_64bit_targets:
fpscr_field_length = 16
else:
fpscr_field_length = 8
pr("fpscr = 0x%.*x " % (fpscr_field_length, fpscr));
pr("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s %s\n" %
(iff(fpscr & 0x80000000, "FX ", ""),
iff(fpscr & 0x40000000, "FEX ", ""),
iff(fpscr & 0x20000000, "VX ", ""),
iff(fpscr & 0x10000000, "OX ", ""),
iff(fpscr & 0x08000000, "UX ", ""),
iff(fpscr & 0x04000000, "ZX ", ""),
iff(fpscr & 0x02000000, "XX ", ""),
iff(fpscr & 0x01000000, "VXSNAN ", ""),
iff(fpscr & 0x00800000, "VXISI ", ""),
iff(fpscr & 0x00400000, "VXIDI ", ""),
iff(fpscr & 0x00200000, "VXZDZ ", ""),
iff(fpscr & 0x00100000, "VXIMZ ", ""),
iff(fpscr & 0x00080000, "VXVC ", ""),
iff(fpscr & 0x00040000, "FR ", ""),
iff(fpscr & 0x00020000, "FI ", ""),
("FPRF[%s%s%s%s%s] " %
(iff (fpscr & 0x00010000, "C", ""),
iff (fpscr & 0x00008000, "<", ""),
iff (fpscr & 0x00004000, ">", ""),
iff (fpscr & 0x00002000, "=", ""),
iff (fpscr & 0x00001000, "?", ""))),
iff(fpscr & 0x00000400, "VXSOFT ", ""),
iff(fpscr & 0x00000200, "VXSQRT ", ""),
iff(fpscr & 0x00000100, "VXCVI ", ""),
iff(fpscr & 0x00000080, "VE ", ""),
iff(fpscr & 0x00000040, "OE ", ""),
iff(fpscr & 0x00000020, "UE ", ""),
iff(fpscr & 0x00000010, "ZE ", ""),
iff(fpscr & 0x00000008, "XE ", ""),
iff(fpscr & 0x00000004, "NI ", ""),
round_kind[fpscr & 3]));
