def build(self): logger.debug('build() *Entered*') super(SimulatorIcarus, self).build() #Build VPI modules for vpi_module in self.vpi_modules: args = [] args += ['--name=' + vpi_module['name']] args += [s for s in vpi_module['libs']] args += ['-I' + s for s in vpi_module['include_dirs']] args += vpi_module['src_files'] Launcher('iverilog-vpi', args, stderr=open( os.path.join(self.sim_root, vpi_module['name'] + '.log'), 'w'), cwd=os.path.join(self.sim_root), errormsg="Failed to compile VPI library " + vpi_module['name']).run() #Build simulation model args = [] args += ['-s', self.toplevel] args += ['-c', 'icarus.scr'] args += ['-o', 'fusesoc.elf'] args += self.iverilog_options Launcher('iverilog', args, cwd=self.sim_root, errormsg="Failed to compile Icarus Simulation model").run() logger.debug('build() -Done-')
def build(self): super(Modelsim, self).build() #FIXME: Handle failures. Save stdout/stderr. Launcher(self.model_tech + '/vlib', ['work'], cwd=self.sim_root, errormsg="Failed to create library 'work'").run() logfile = os.path.join(self.sim_root, 'vlog.log') args = [] args += ['-f', self.cfg_file] args += ['-quiet'] args += ['-l', logfile] args += self.vlog_options Launcher( self.model_tech + '/vlog', args, cwd=self.sim_root, errormsg= "Failed to compile simulation model. Compile log is available in " + logfile).run() for vpi_module in self.vpi_modules: objs = [] for src_file in vpi_module['src_files']: args = [] args += ['-c'] args += ['-std=c99'] args += ['-fPIC'] args += ['-fno-stack-protector'] args += ['-g'] args += ['-m32'] args += ['-DMODELSIM_VPI'] args += ['-I' + self.model_tech + '/../include'] args += ['-I' + s for s in vpi_module['include_dirs']] args += [src_file] Launcher('gcc', args, cwd=self.sim_root, errormsg="Compilation of " + src_file + "failed").run() object_files = [ os.path.splitext(os.path.basename(s))[0] + '.o' for s in vpi_module['src_files'] ] args = [] args += ['-shared'] args += ['-E'] args += ['-melf_i386'] args += ['-o', vpi_module['name']] args += object_files args += [s for s in vpi_module['libs']] Launcher('ld', args, cwd=self.sim_root, errormsg="Linking of " + vpi_module['name'] + " failed").run()
def build_SysC(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() args = ['-I.'] args += ['-MMD'] args += ['-I'+src_root] args += ['-I'+s for s in self.include_dirs] args += ['-Iobj_dir'] args += ['-I'+os.path.join(verilator_root,'include')] args += ['-I'+os.path.join(verilator_root,'include', 'vltstd')] args += ['-DVL_PRINTF=printf'] args += ['-DVM_TRACE=1'] args += ['-DVM_COVERAGE=0'] if os.getenv('SYSTEMC_INCLUDE'): args += ['-I'+os.getenv('SYSTEMC_INCLUDE')] if os.getenv('SYSTEMC'): args += ['-I'+os.path.join(os.getenv('SYSTEMC'),'include')] args += ['-Wno-deprecated'] if os.getenv('SYSTEMC_CXX_FLAGS'): args += [os.getenv('SYSTEMC_CXX_FLAGS')] args += ['-c'] args += ['-g'] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('g++', args + [os.path.join(src_root, core, src_file)], cwd=sim_root) print(l) l.run()
def build_SysC(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() args = ['-I.'] args += ['-MMD'] args += ['-I' + src_root] args += ['-I' + s for s in self.include_dirs] args += ['-Iobj_dir'] args += ['-I' + os.path.join(verilator_root, 'include')] args += ['-I' + os.path.join(verilator_root, 'include', 'vltstd')] args += ['-DVL_PRINTF=printf'] args += ['-DVM_TRACE=1'] args += ['-DVM_COVERAGE=0'] if os.getenv('SYSTEMC_INCLUDE'): args += ['-I' + os.getenv('SYSTEMC_INCLUDE')] if os.getenv('SYSTEMC'): args += ['-I' + os.path.join(os.getenv('SYSTEMC'), 'include')] args += ['-Wno-deprecated'] if os.getenv('SYSTEMC_CXX_FLAGS'): args += [os.getenv('SYSTEMC_CXX_FLAGS')] args += ['-c'] args += ['-g'] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('g++', args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr=open(os.path.join(sim_root, 'g++.err.log'), 'a')) if Config().verbose: pr_info(" SystemC compilation working dir: " + sim_root) pr_info(" SystemC compilation command: g++ " + ' '.join(args) + ' ' + os.path.join(src_root, core, src_file)) l.run()
def build_SysC(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() args = ['-I.'] args += ['-MMD'] args += ['-I'+src_root] args += ['-I'+s for s in self.include_dirs] args += ['-Iobj_dir'] args += ['-I'+os.path.join(verilator_root,'include')] args += ['-I'+os.path.join(verilator_root,'include', 'vltstd')] args += ['-DVL_PRINTF=printf'] args += ['-DVM_TRACE=1'] args += ['-DVM_COVERAGE=0'] if os.getenv('SYSTEMC_INCLUDE'): args += ['-I'+os.getenv('SYSTEMC_INCLUDE')] if os.getenv('SYSTEMC'): args += ['-I'+os.path.join(os.getenv('SYSTEMC'),'include')] args += ['-Wno-deprecated'] if os.getenv('SYSTEMC_CXX_FLAGS'): args += [os.getenv('SYSTEMC_CXX_FLAGS')] args += ['-c'] args += ['-g'] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('g++', args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr = open(os.path.join(sim_root, 'g++.err.log'),'a')) if Config().verbose: pr_info(" SystemC compilation working dir: " + sim_root) pr_info(" SystemC compilation command: g++ " + ' '.join(args) + ' ' + os.path.join(src_root, core, src_file)) l.run()
def update(cm, args): libraries = args.libraries for root in cm.get_cores_root(): if not root in cm.config.cores_root: # This is a library - handled differently continue if os.path.exists(root) and (not libraries or root in libraries): args = ['-C', root, 'config', '--get', 'remote.origin.url'] repo_root = "" try: repo_root = subprocess.check_output(['git'] + args).decode("utf-8") if repo_root.strip() in [repo[1] for repo in REPOS]: logger.info("Updating '{}'".format(root)) args = ['-C', root, 'pull'] Launcher('git', args).run() except subprocess.CalledProcessError: pass for (name, library) in cm.config.libraries.items(): if os.path.exists(library['location']) and \ (name in libraries or \ library['location'] in libraries or \ library['auto-sync']): logger.info("Updating '{}'".format(name)) args = ['-C', library['location'], 'pull'] try: Launcher('git', args).run() except subprocess.CalledProcessError: pass
def build(self): super(Ghdl, self).build() (src_files, incdirs) = self._get_fileset_files(['sim', 'ghdl']) cmd = 'ghdl' for f in src_files: args = ['-a'] args += self.analyze_options[:] _supported = True if not f.logical_name: f.logical_name = 'work' if f.file_type == "vhdlSource": pass elif f.file_type == "vhdlSource-87": args += ['--std=87'] elif f.file_type == "vhdlSource-93": args += ['--std=93'] elif f.file_type == "vhdlSource-2008": args += ['--std=08'] else: _s = "{} has unknown file type '{}'" pr_warn(_s.format(f.name, f.file_type)) _supported = False if _supported: args += ['--work=' + f.logical_name] args += [f.name] Launcher(cmd, args, cwd=self.sim_root, errormsg="Failed to analyze {}".format(f.name)).run() Launcher(cmd, ['-e', self.toplevel], cwd=self.sim_root, errormsg="Failed to elaborate {}".format( self.toplevel)).run()
def build(self): super(Icarus, self).build() #Build VPI modules for vpi_module in self.vpi_modules: args = [] args += ['--name='+vpi_module['name']] args += [s for s in vpi_module['libs']] args += ['-I' + s for s in vpi_module['include_dirs']] args += vpi_module['src_files'] Launcher('iverilog-vpi', args, stderr = open(os.path.join(self.work_root,vpi_module['name']+'.log'),'w'), cwd = os.path.join(self.work_root), errormsg = "Failed to compile VPI library " + vpi_module['name']).run() #Build simulation model args = [] args += ['-s'+s for s in self.toplevel.split(' ')] args += ['-c', 'icarus.scr'] args += ['-o', 'fusesoc.elf'] for key, value in self.vlogdefine.items(): args += ['-D{}={}'.format(key, self._param_value_str(value, strings_in_quotes=True))] for key, value in self.vlogparam.items(): args += ['-P{}.{}={}'.format(self.toplevel, key, self._param_value_str(value, strings_in_quotes=True))] if self.system.icarus is not None: args += self.system.icarus.iverilog_options Launcher('iverilog', args, cwd = self.work_root, errormsg = "Failed to compile Icarus Simulation model").run()
def _checkout(self, local_dir): #TODO : Sanitize URL pr_info("Checking out " + self.repo + " to " + local_dir) args = ['clone', '-q', self.repo, local_dir] Launcher('git', args).run() if self.version: args = ['-C', local_dir, 'checkout', '-q', self.version] Launcher('git', args).run()
def _checkout(self, local_dir): version = self.config.get('version', None) #TODO : Sanitize URL repo = self.config.get('repo') logger.info("Checking out " + repo + " to " + local_dir) args = ['clone', '-q', repo, local_dir] Launcher('git', args).run() if version: args = ['-C', local_dir, 'checkout', '-q', version] Launcher('git', args).run()
def _checkout(self, local_dir): version = self.config.get("version", None) # TODO : Sanitize URL repo = self.config.get("repo") logger.info("Checking out " + repo + " to " + local_dir) args = ["clone", "-q", repo, local_dir] Launcher("git", args).run() if version: args = ["-C", local_dir, "checkout", "-q", version] Launcher("git", args).run()
def build_C(self, core, sim_root, src_root): args = ['-c'] args += ['-std=c99'] args += ['-I'+src_root] args += ['-I'+os.path.join(src_root, core, s) for s in self.include_dirs] for src_file in self.src_files: print("Compiling " + src_file) l = Launcher('gcc', args + [os.path.join(src_root, core, src_file)], cwd=sim_root) print(l) l.run()
def build(self): super(Ghdl, self).build() (src_files, incdirs) = self._get_fileset_files() cmd = 'ghdl' # ghdl does not support mixing incompatible versions # specifying 93c as std should allow 87 syntax # 2008 can't be combined so try to parse everthing with 08 std has87 = has93 = has08 = False for f in src_files: if f.file_type == "vhdlSource-87": has87 = True elif f.file_type == "vhdlSource-93": has93 = True elif f.file_type == "vhdlSource-2008": has08 = True stdarg = [] if has08: if has87 or has93: logger.warning( "ghdl can't mix vhdlSource-2008 with other standard version\n" + "Trying with treating all as vhdlSource-2008") stdarg = ['--std=08'] elif has87 and has93: stdarg = ['--std=93c'] elif has87: stdarg = ['--std=87'] elif has93: stdarg = ['--std=93'] _vhdltypes = ("vhdlSource", "vhdlSource-87", "vhdlSource-93", "vhdlSource-2008") for f in src_files: args = ['-a'] + stdarg if 'analyze_options' in self.tool_options: args += self.tool_options['analyze_options'][:] if f.file_type in _vhdltypes: if f.logical_name: args += ['--work=' + f.logical_name] args += [f.name] Launcher(cmd, args, cwd=self.work_root, errormsg="Failed to analyze {}".format(f.name)).run() else: _s = "{} has unknown file type '{}'" logger.warning(_s.format(f.name, f.file_type)) Launcher(cmd, ['-e'] + stdarg + [self.toplevel], cwd=self.work_root, errormsg="Failed to elaborate {}".format( self.toplevel)).run()
def build_C(self, core, sim_root, src_root): args = ['-c'] args += ['-std=c99'] args += ['-I'+src_root] args += ['-I'+os.path.join(src_root, core, s) for s in self.include_dirs] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('gcc', args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr = open(os.path.join(sim_root, src_file+'.err.log'),'w'), stdout = open(os.path.join(sim_root, src_file+'.out.log'),'w')) l.run()
def build_CPP(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() if verilator_root is None: verilator_root = utils.get_verilator_root() args = ['-c'] args += ['-I'+src_root] args += ['-I'+os.path.join(src_root, core, s) for s in self.include_dirs] args += ['-I'+os.path.join(verilator_root,'include')] args += ['-I'+os.path.join(verilator_root,'include', 'vltstd')] for src_file in self.src_files: print("Compiling " + src_file) l = Launcher('g++', args + [os.path.join(src_root, core, src_file)], cwd=sim_root) print(l) l.run()
def update_library(library): logger.info("Updating library {}".format(library['location'])) git_args = ['-C', library['location'], 'pull'] try: Launcher('git', git_args).run() except subprocess.CalledProcessError as e: raise RuntimeError(str(e))
def _checkout(self, local_dir): core_files = self.config.get('core_files') if not os.path.isdir(local_dir): os.mkdir(local_dir) for f_output, f_input in core_files.items(): core_basename = os.path.basename(f_input) core_dirname = os.path.dirname(f_input) f_src = os.path.join(local_dir, core_dirname) + '/' + core_basename f_dst = os.path.join(local_dir, f_output) if os.path.exists(f_src): d_dst = os.path.dirname(f_dst) if not os.path.exists(d_dst): os.makedirs(d_dst) else: logger.error('Cannot find file %s' % f_src) for out_filename, f_name in core_files.items(): core_basename = os.path.basename(f_name) core_dirname = os.path.dirname(f_name) input_json_name = os.path.join(local_dir, core_dirname) + '/' + core_basename gen_build_rom_file = local_dir + '/' + out_filename logger.info("Using BuildRom to generate core " + input_json_name) logger.info("Using BuildRom to gen " + gen_build_rom_file) # config_rom args args = ['-v', gen_build_rom_file, '-j', input_json_name] Launcher('build_rom.py', args, cwd=local_dir).run()
def build(self): super(Xsim, self).build() #Check if any VPI modules are present and display warning if len(self.vpi_modules) > 0: modules = [m['name'] for m in self.vpi_modules] pr_err('VPI modules not supported by Xsim: %s' % ', '.join(modules)) #Build simulation model args = [] args += [self.toplevel] args += ['--prj', 'xsim.prj'] # list of design files args += ['--timescale', '1ps/1ps' ] # default timescale to prevent error if unspecified args += ['--snapshot', 'fusesoc'] # name of the design to simulate args += ['--debug', 'typical'] # capture waveforms for include_dir in self.incdirs: args += ['-i', include_dir] args += self.xsim_options Launcher('xelab', args, cwd=self.sim_root, errormsg="Failed to compile Xsim simulation model").run()
def _checkout(self, local_dir): script_file = self.config.get("script_file") project_file = self.config.get("project_file") extra_files = self.config.get("extra_files") logger.info( "Using Xilinx Vivado to generate LogiCORE(tm) project " + project_file ) if not os.path.isdir(local_dir): os.mkdir(local_dir) src_files = [script_file, project_file] if extra_files: src_files += extra_files.split() for f in src_files: f_src = os.path.join(self.core_root, f) f_dst = os.path.join(local_dir, f) if os.path.exists(f_src): d_dst = os.path.dirname(f_dst) if not os.path.exists(d_dst): os.makedirs(d_dst) shutil.copyfile(f_src, f_dst) else: logger.error("Cannot find file %s" % f_src) args = ["-mode", "batch", "-source", script_file] Launcher("vivado", args, cwd=local_dir).run()
def run(self, args): parser = argparse.ArgumentParser(prog ='fusesoc sim '+self.system.name, conflict_handler='resolve') for name in self.cores: core = self.cm.get_core(name) if core.plusargs: core.plusargs.add_arguments(parser) p = parser.parse_args(args) self.plusargs = [] for key,value in vars(p).items(): if value == True: self.plusargs += [key] elif value == False or value is None: pass else: self.plusargs += [key+'='+str(value[0])] for script in self.system.pre_run_scripts: script = os.path.abspath(os.path.join(self.system.core_root, script)) pr_info("Running " + script); try: Launcher(script, cwd = self.sim_root, env = self.env, shell=True).run() except RuntimeError: pr_err("Error: script " + script + " failed")
def run(self, args): super(Modelsim, self).run(args) #FIXME: Handle failures. Save stdout/stderr vpi_options = [] for vpi_module in self.vpi_modules: vpi_options += ['-pli', vpi_module['name']] logfile = os.path.join(self.sim_root, 'vsim.log') args = [] args += ['-quiet'] args += ['-c'] args += ['-do', 'run -all'] args += ['-l', logfile] args += self.vsim_options args += vpi_options args += ['work.' + self.toplevel] args += ['+' + s for s in self.plusargs] Launcher( self.model_tech + '/vsim', args, cwd=self.sim_root, errormsg="Simulation failed. Simulation log is available in " + logfile).run() super(Modelsim, self).done(args)
def elaborate(work_root, top_name): ''' Elaborate the design using ghdl. ''' Launcher('ghdl', ['-e', '--std=08'] + [top_name], cwd=work_root, errormsg="Failed to elaborate {}".format(top_name)).run()
def run(self, args): super(Modelsim, self).run(args) #FIXME: Handle failures. Save stdout/stderr vpi_options = [] for vpi_module in self.vpi_modules: vpi_options += ['-pli', vpi_module['name']] args = self.run_default_args args += self.vsim_options args += vpi_options args += [self.toplevel] # Plusargs for key, value in self.plusarg.items(): args += ['+{}={}'.format(key, value)] #Top-level parameters for key, value in self.vlogparam.items(): args += ['-g{}={}'.format(key, value)] Launcher(self.model_tech+'/vsim', args, cwd = self.sim_root, errormsg = "Simulation failed. Simulation log is available in '{}'".format(os.path.join(self.sim_root, 'transcript'))).run() super(Modelsim, self).done(args)
def init_library(library): logger.info("Cloning library into {}".format(library['location'])) git_args = ['clone', library['sync-uri'], library['location']] try: Launcher('git', git_args).run() except subprocess.CalledProcessError as e: raise RuntimeError(str(e))
def _checkout(self, local_dir): logger.warning( "The coregen provider is deprecated and will be removed. Consider using a generator for this instead" ) script_file = self.config.get("script_file") project_file = self.config.get("project_file") extra_files = self.config.get("extra_files") logger.info("Using Coregen to generate project " + project_file) if not os.path.isdir(local_dir): os.makedirs(local_dir) src_files = [script_file, project_file] if extra_files: src_files += extra_files.split() for f in src_files: f_src = os.path.join(self.core_root, f) f_dst = os.path.join(local_dir, f) if os.path.exists(f_src): d_dst = os.path.dirname(f_dst) if not os.path.exists(d_dst): os.makedirs(d_dst) shutil.copyfile(f_src, f_dst) else: logger.error("Cannot find file %s" % f_src) args = ["-r", "-b", script_file, "-p", project_file] Launcher("coregen", args, cwd=local_dir).run()
def build(self): super(Isim, self).build() #Check if any VPI modules are present and display warning if len(self.vpi_modules) > 0: modules = [m['name'] for m in self.vpi_modules] logger.error('VPI modules not supported by Isim: %s' % ', '.join(modules)) #Build simulation model args = [] args += self.toplevel.split() args += ['-prj', 'isim.prj'] args += ['-o', 'fusesoc.elf'] for include_dir in self.incdirs: args += ['-i', include_dir] for key, value in self.vlogparam.items(): args += ['--generic_top', '{}={}'.format(key, value)] if self.system.isim is not None: args += self.system.isim.isim_options Launcher('fuse', args, cwd=self.work_root, errormsg="Failed to compile Isim simulation model").run()
def _checkout(self, local_dir): repo_name = self.config.get("repo_name") repo_path = REPO_PATH.format(repo_name, repo_name, self.config.get("repo_root")) revision_number = self.config.get("revision") logger.info("Downloading " + repo_name + " from OpenCores") if is_mingw(): logger.debug("Using cygpath translation") local_dir = cygpath(local_dir) Launcher( "svn", [ "co", "-q", "--no-auth-cache", "-r", revision_number, "--username", "orpsoc", "--password", "orpsoc", repo_path, local_dir, ], ).run()
def update_library(library): git_args = ["-C", library.location, "pull"] try: Git._checkout_library_version(library) Launcher("git", git_args).run() except subprocess.CalledProcessError as e: raise RuntimeError(str(e))
def build_C(self, core, sim_root, src_root): args = ['-c'] args += ['-std=c99'] args += ['-I'+src_root] args += ['-I'+os.path.join(src_root, core, s) for s in self.include_dirs] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('gcc', args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr = open(os.path.join(sim_root, 'gcc.err.log'),'a'), stdout = open(os.path.join(sim_root, 'gcc.out.log'),'a')) if Config().verbose: pr_info(" C compilation working dir: " + sim_root) pr_info(" C compilation command: gcc " + ' '.join(args) + ' ' + os.path.join(src_root, core, src_file)) l.run()
def init_library(library): logger.info("Cloning library into {}".format(library.location)) git_args = ["clone", library.sync_uri, library.location] try: Launcher("git", git_args).run() except subprocess.CalledProcessError as e: raise RuntimeError(str(e))
def build(self): super(Xsim, self).build() #Check if any VPI modules are present and display warning if len(self.vpi_modules) > 0: modules = [m['name'] for m in self.vpi_modules] logger.error('VPI modules not supported by Xsim: %s' % ', '.join(modules)) #Build simulation model args = [] args += [self.toplevel] args += ['--prj', 'xsim.prj'] # list of design files args += ['--timescale', '1ps/1ps' ] # default timescale to prevent error if unspecified args += ['--snapshot', 'fusesoc'] # name of the design to simulate args += ['--debug', 'typical'] # capture waveforms for include_dir in self.incdirs: args += ['-i', include_dir] for key, value in self.vlogparam.items(): args += [ '--generic_top', '{}={}'.format(key, self._param_value_str(value)) ] if self.system.xsim is not None: args += self.system.xsim.xsim_options Launcher('xelab', args, cwd=self.work_root, errormsg="Failed to compile Xsim simulation model").run()
def build(self): super(Icarus, self).build() Launcher('make', cwd=self.work_root, stdout=open(os.path.join(self.work_root, 'build.log'), 'w')).run()
def _checkout(self, local_dir): core_file = self.config.get('core_file') gen_file_type = self.config.get('generated_file_type') core_file_name, core_file_ext = os.path.splitext(core_file) # We only support verilog or vhdl generated files if gen_file_type is not None and \ gen_file_type != 'verilogSource' and \ gen_file_type != 'vhdlSource': raise SyntaxError( "Unsuported option '{}' in Cheby provider section".format( gen_file_type)) gen_vhdl_file = local_dir + '/' + core_file_name + '.vhd' gen_verilog_file = local_dir + '/' + core_file_name + '.v' logger.info("Using Cheby to generate core " + core_file) if not os.path.isdir(local_dir): os.mkdir(local_dir) src_files = [core_file] for f in src_files: f_src = os.path.join(self.core_root, f) f_dst = os.path.join(local_dir, f) if os.path.exists(f_src): d_dst = os.path.dirname(f_dst) if not os.path.exists(d_dst): os.makedirs(d_dst) shutil.copyfile(f_src, f_dst) else: logger.error('Cannot find file %s' % f_src) # Cheby does not support native Verilog generation, so the only option # is to generate a VHDL file and then convert it, if needed. with open(gen_vhdl_file, 'w+') as f: args = ['--gen-vhdl', core_file] Launcher('cheby', args, cwd=local_dir, stdout=f).run() if gen_file_type is None or gen_file_type == 'verilogSource': with open(gen_verilog_file, 'w+') as f: args = [gen_vhdl_file, gen_verilog_file] Launcher('vhd2vl', args, cwd=local_dir).run() os.remove(gen_vhdl_file) # vhd2vl does not convert between true/false in VHDL to 1/0 in Verilog f = fileinput.input(gen_verilog_file, inplace=True) for line in f: print(line.replace('true', '1').replace('false', '0'), end='') f.close()
def run_main(self): if not os.getenv('ALDEC_PATH'): raise RuntimeError("Environment variable ALDEC_PATH was not found. It should be set to Riviera Pro install path. Please source <Riviera Pro install path>/etc/setenv to set it") args = ['-c', '-quiet', '-do', 'fusesoc_run.tcl'] Launcher('vsim', args, cwd = self.work_root, errormsg = "Simulation failed. Simulation log is available in '{}'".format(os.path.join(self.work_root, 'transcript'))).run()
def build_main(self): args = ['-c', '-do', 'do fusesoc_main.tcl; exit'] Launcher( 'vsim', args, cwd=self.work_root, errormsg="Failed to build simulation model. Log is available in '{}'" .format(os.path.join(self.work_root, 'transcript'))).run()
def build_C(self, core, sim_root, src_root): args = ["-c"] args += ["-std=c99"] args += ["-I" + src_root] args += ["-I" + os.path.join(src_root, core, s) for s in self.include_dirs] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher( "gcc", args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr=open(os.path.join(sim_root, "gcc.err.log"), "a"), stdout=open(os.path.join(sim_root, "gcc.out.log"), "a"), ) if Config().verbose: pr_info(" C compilation working dir: " + sim_root) pr_info(" C compilation command: gcc " + " ".join(args) + " " + os.path.join(src_root, core, src_file)) l.run()
def build_CPP(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() if verilator_root is None: verilator_root = utils.get_verilator_root() args = ['-c'] args += ['-I'+src_root] args += ['-I'+os.path.join(src_root, core, s) for s in self.include_dirs] args += ['-I'+os.path.join(verilator_root,'include')] args += ['-I'+os.path.join(verilator_root,'include', 'vltstd')] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher('g++', args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr = open(os.path.join(sim_root, 'g++.err.log'),'a')) if Config().verbose: pr_info(" C++ compilation working dir: " + sim_root) pr_info(" C++ compilation command: g++ " + ' '.join(args) + ' ' + os.path.join(src_root, core, src_file)) l.run()
def build(self, core, sim_root, src_root): if self.source_type == "C" or self.source_type == "": self.build_C(core, sim_root, src_root) elif self.source_type == "CPP": self.build_CPP(core, sim_root, src_root) elif self.source_type == "systemC": self.build_SysC(core, sim_root, src_root) else: raise Source(self.source_type) if self._object_files: args = [] args += ["rvs"] args += [core + ".a"] args += self._object_files l = Launcher("ar", args, cwd=sim_root) if Config().verbose: pr_info(" linker working dir: " + sim_root) pr_info(" linker command: ar " + " ".join(args)) l.run() print()
def build(self, core, sim_root, src_root): if self.source_type == 'C' or self.source_type == '': self.build_C(core, sim_root, src_root) elif self.source_type == 'CPP': self.build_CPP(core, sim_root, src_root) elif self.source_type == 'systemC': self.build_SysC(core, sim_root, src_root) else: raise Source(self.source_type) if self._object_files: args = [] args += ['rvs'] args += [core+'.a'] args += self._object_files l = Launcher('ar', args, cwd=sim_root) if Config().verbose: pr_info(" linker working dir: " + sim_root) pr_info(" linker command: ar " + ' '.join(args)) l.run() print()
def build_SysC(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() args = ["-I."] args += ["-MMD"] args += ["-I" + src_root] args += ["-I" + s for s in self.include_dirs] args += ["-Iobj_dir"] args += ["-I" + os.path.join(verilator_root, "include")] args += ["-I" + os.path.join(verilator_root, "include", "vltstd")] args += ["-DVL_PRINTF=printf"] args += ["-DVM_TRACE=1"] args += ["-DVM_COVERAGE=0"] if os.getenv("SYSTEMC_INCLUDE"): args += ["-I" + os.getenv("SYSTEMC_INCLUDE")] if os.getenv("SYSTEMC"): args += ["-I" + os.path.join(os.getenv("SYSTEMC"), "include")] args += ["-Wno-deprecated"] if os.getenv("SYSTEMC_CXX_FLAGS"): args += [os.getenv("SYSTEMC_CXX_FLAGS")] args += ["-c"] args += ["-g"] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher( "g++", args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr=open(os.path.join(sim_root, "g++.err.log"), "a"), ) if Config().verbose: pr_info(" SystemC compilation working dir: " + sim_root) pr_info( " SystemC compilation command: g++ " + " ".join(args) + " " + os.path.join(src_root, core, src_file) ) l.run()
def build_CPP(self, core, sim_root, src_root): verilator_root = utils.get_verilator_root() if verilator_root is None: verilator_root = utils.get_verilator_root() args = ["-c"] args += ["-I" + src_root] args += ["-I" + os.path.join(src_root, core, s) for s in self.include_dirs] args += ["-I" + os.path.join(verilator_root, "include")] args += ["-I" + os.path.join(verilator_root, "include", "vltstd")] for src_file in self.src_files: pr_info("Compiling " + src_file) l = Launcher( "g++", args + [os.path.join(src_root, core, src_file)], cwd=sim_root, stderr=open(os.path.join(sim_root, "g++.err.log"), "a"), ) if Config().verbose: pr_info(" C++ compilation working dir: " + sim_root) pr_info( " C++ compilation command: g++ " + " ".join(args) + " " + os.path.join(src_root, core, src_file) ) l.run()