def main():
cfg.setup()
cfg.sv = "lram.v"
def per_word(w):
nonrouting.fuzz_ip_word_setting(cfg, "INITVAL_{:02X}".format(w), 5120, lambda b: dict(a="{:02X}".format(w), v="0x{:01280x}".format(bin2dec(b))))
# Only fuzz a couple of init values to stop the database getting massive - we can derive the rest
fuzzloops.parallel_foreach(range(0x2), per_word)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
cfg = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
if cfg.ncl == "empty_25k.ncl":
cfg.ncl = "dcs_25k.ncl"
elif cfg.ncl == "empty_85k.ncl":
cfg.ncl = "dcs_85k.ncl"
else:
cfg.ncl = "dcs.ncl"
for loc in ("DCS0", "DCS1"):
def get_substs(dcsmode="POS"):
if dcsmode == "NONE":
comment = "//"
else:
comment = ""
return dict(site=loc, comment=comment, dcsmode=dcsmode)
nonrouting.fuzz_enum_setting(cfg, "{}.DCSMODE".format(loc), [
"NONE", "POS", "NEG", "CLK0", "CLK1", "CLK0_LOW", "CLK0_HIGH",
"CLK1_LOW", "CLK1_HIGH", "LOW", "HIGH"
], lambda x: get_substs(dcsmode=x), empty_bitfile, False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
cfg.setup()
cfg.sv = "pcie.v"
empty = cfg.build_design(cfg.sv, get_substs("GSR", "ENABLED"))
words, enums = get_params.get_params(
os.path.join(os.environ['RADIANTDIR'], "cae_library", "simulation",
"verilog", "lifcl", "PCIE.v"))
# force words with non-zero default to zero...
for n, w, d in words:
if int(d, 2) != 0:
defaults.append((n, "0b{}".format("0" * w)))
def per_word(w):
name, width, default = w
nonrouting.fuzz_ip_word_setting(
cfg,
name,
width,
lambda b: get_substs(name, str(bin2bin(b))),
"",
default=[d == "1" for d in reversed(default)])
fuzzloops.parallel_foreach(words, per_word)
def per_enum(e):
name, options = e
nonrouting.fuzz_ip_enum_setting(cfg, empty, name, options,
lambda x: get_substs(name, x), "")
fuzzloops.parallel_foreach(enums, per_enum)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(net, value):
if net == value:
settings = "{}=#SIG".format(net, net)
else:
settings = "{}=#INV".format(net)
return dict(loc=loc, mode=mode, settings=settings,
cmodel=cellmodel)
loc, mult, cfg = job
cellmodel = loc.split("_")[0]
mode = "MULT18X18D" if cellmodel == "MULT18" else "ALU54B"
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dspconfig.ncl"
for port in ["CLK", "CE", "RST"]:
for i in range(4):
sig = port + str(i)
nonrouting.fuzz_enum_setting(cfg, "{}.{}MUX".format(mult, sig), [sig, "INV"],
lambda x: get_substs(sig, x), empty_bitfile,
False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ip.v"
def per_site(s):
site, prim = s
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False, extra_sigs=""):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}{}".format(mode, kv[0], val, extra_sigs)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, prim=prim, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "{}.MODE".format(prim), ["NONE", prim],
lambda x: get_substs(mode=x), False,
desc="{} primitive mode".format(prim))
for name, values, desc in settings[prim]:
nonrouting.fuzz_enum_setting(cfg, empty, "{}.{}".format(prim, name), values,
lambda x: get_substs(mode=prim, kv=(name, x)), False,
desc=desc)
if prim in words:
for name, width, desc in words[prim]:
nonrouting.fuzz_word_setting(cfg, "{}.{}".format(prim, name), width,
lambda x: get_substs(mode=prim, kv=(name, "0b" + "".join(reversed(["1" if b else "0" for b in x])))),
desc=desc)
fuzzloops.parallel_foreach(sites, per_site)
def build_and_add(designs,
density="45",
inc_cell=cell_timings.include_cell,
rw_cell_func=cell_timings.rewrite_celltype,
rw_pin_func=cell_timings.rewrite_pin):
jobs = []
sdfs = dict()
for des in designs:
jobs += timing_configs(
path.basename(des).replace(".v", ""), des, density)
for job in jobs:
grade, cfg = job
sdfs[grade] = []
def per_job(job):
grade, cfg = job
cfg.setup(skip_specimen=True)
bitf = cfg.build_design(cfg.ncl, {}, backanno=True, substitute=False)
sdf = bitf.replace(".bit", ".sdf")
sdfs[grade].append(sdf)
fuzzloops.parallel_foreach(jobs, per_job)
for grade in sdfs.keys():
db = timing_dbs.cells_db_path("ECP5", grade)
for sdf in sdfs[grade]:
cell_timings.add_sdf_to_database(db,
sdf,
include_cell_predicate=inc_cell,
rewrite_cell_func=rw_cell_func,
rewrite_pin_func=rw_pin_func)
def main():
dcc_tiles = ["CIB_R28C0:LMID", "CIB_R28C87:RMID_DLY20", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C50:BMID_1_ECLK_2",
"CIB_R0C49:TMID_0", "CIB_R0C50:TMID_1", "CIB_R29C49:CMUX_0", "CIB_R29C50:CMUX_1", "CIB_R38C49:CMUX_2", "CIB_R38C50:CMUX_3"]
dcs_tiles = ["CIB_R29C49:CMUX_0", "CIB_R29C50:CMUX_1", "CIB_R38C49:CMUX_2", "CIB_R38C50:CMUX_3"]
dcc_prims = ["DCC_L{}".format(i) for i in range(12)] + \
["DCC_R{}".format(i) for i in range(12)] + \
["DCC_T{}".format(i) for i in range(16)] + \
["DCC_B{}".format(i) for i in range(18)] + \
["DCC_C{}".format(i) for i in range(4)]
dcs_prims = ["DCS0", ]
def per_site(site):
if site.startswith("DCC"):
cfg = FuzzConfig(job=site, device="LIFCL-40", sv="../shared/empty_40.v", tiles=dcc_tiles)
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "dcc.v"
def get_substs(dccen):
return dict(site=site, dccen=dccen)
nonrouting.fuzz_enum_setting(cfg, empty, "{}.DCCEN".format(site), ["0", "1"],
lambda x: get_substs(x), False,
desc="DCC bypassed (0) or used as gate (1)")
else:
assert site.startswith("DCS")
cfg = FuzzConfig(job=site, device="LIFCL-40", sv="../shared/empty_40.v", tiles=dcs_tiles)
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "dcs.v"
def get_substs(dcsmode):
return dict(site=site, dcsmode=dcsmode)
nonrouting.fuzz_enum_setting(cfg, empty, "{}.DCSMODE".format(site),
["GND", "DCS", "DCS_1", "BUFGCECLK0", "BUFGCECLK0_1", "BUFGCECLK1", "BUFGCECLK1_1", "BUF0", "BUF1", "VCC"],
lambda x: get_substs(x), False,
desc="clock selector mode")
fuzzloops.parallel_foreach(dcc_prims + dcs_prims, per_site)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "mkmux.ncl"
def per_slice(slicen):
def get_substs(m0mux="M0", m1mux="M1", f_mode="F"):
if m0mux == "OFF":
s_m0mux = "#OFF"
else:
s_m0mux = m0mux
return dict(slice=slicen, m0mux=s_m0mux, m1mux=m1mux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.M0MUX".format(slicen),
["M0", "OFF", "0"],
lambda x: get_substs(m0mux=x),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.M1MUX".format(slicen),
["M1", "OFF", "0"],
lambda x: get_substs(m1mux=x),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.F0".format(slicen),
["F", "OFF", "0"],
lambda x: get_substs(f_mode=x),
empty_bitfile, False)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
pytrellis.load_database("../../database")
pytrellis.load_database("../../database")
def per_job(job):
def get_substs(mode="IREG_OREG", program=[]):
if mode == "NONE":
comment = "//"
program = ""
else:
comment = ""
program = "program " + "\n\t\t\t".join(
['"' + _ + ' "' for _ in program])
return dict(loc=loc, mode=mode, program=program, comment=comment)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
modes = [
"NONE", "IREG_OREG", "IDDRX1_ODDRX1", "IDDRXN", "ODDRXN",
"MIDDRX_MODDRX"
]
tie_program = ["LSRIMUX:0", "LSROMUX:0"]
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.MODE".format(iol), modes,
lambda x: get_substs(mode=x, program=["MODE:" + x] + tie_program),
empty_bitfile, False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(mode=""):
if mode != "NONE":
mode = "ODDRXN:::DDRMODE={}".format(mode)
else:
mode = ""
return dict(loc=loc, mode=mode)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
side = job["side"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.ODDRXN.MODE".format(iol),
["NONE", "ODDRX2", "ODDR71"],
lambda x: get_substs(mode=x),
empty_bitfile, False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "lsr.ncl"
def per_lsr(lsrn):
slices = { "0" : "A",
"1" : "B",
"2" : "C",
"3" : "D"
}
def get_substs(lsrmux="LSR", srmode="LSR_OVER_CE", lsronmux="0"):
if lsrmux == "INV":
lsrmux = "LSR:::LSR=#INV"
return dict(s=slices[lsrn], l=lsrn, lsrmux=lsrmux, srmode=srmode, lsronmux=lsronmux)
nonrouting.fuzz_enum_setting(cfg, "LSR{}.LSRMUX".format(lsrn), ["LSR", "INV"],
lambda x: get_substs(lsrmux=x),
empty_bitfile, True)
nonrouting.fuzz_enum_setting(cfg, "LSR{}.SRMODE".format(lsrn), ["LSR_OVER_CE", "ASYNC"],
lambda x: get_substs(srmode=x),
empty_bitfile, True)
nonrouting.fuzz_enum_setting(cfg, "LSR{}.LSRONMUX".format(lsrn), ["0", "LSRMUX"],
lambda x: get_substs(lsronmux=x),
empty_bitfile, True)
fuzzloops.parallel_foreach(["0", "1", "2", "3"], per_lsr)
def main():
pytrellis.load_database("../../../database")
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(regtype="", regen="OFF", regset="RESET", srmode="ASYNC", regmode="FF", ceimux="1", ceomux="1", datamux="PADDO"):
clkimux = "CLK"
clkomux = "CLK"
if regen == "ON":
reg = "{}:::REGSET={},{}REGMODE={}".format(regtype, regset, "IN" if regtype == "FF" else "OUT", regmode)
if regmode == "LATCH":
if regtype == "FF":
clkimux = "CLK:::CLK=#INV" # clk is inverted for latches
else:
clkomux = "CLK:::CLK=#INV" # clk is inverted for latches
else:
reg = ""
if side in ("T, B"):
s = "S"
else:
s = ""
return dict(loc=loc, reg=reg, s=s, pin=pin, srmode=srmode, clkimux=clkimux, clkomux=clkomux, ceimux=ceimux, ceomux=ceomux, datamux=datamux)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
side = job["side"]
pin = job["pin"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF".format(iol), ["OFF", "ON"],
lambda x: get_substs(regtype="FF", regen=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF.INREGMODE".format(iol), ["FF", "LATCH"],
lambda x: get_substs(regtype="FF", regen="ON", regmode=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF.REGSET".format(iol), ["SET", "RESET"],
lambda x: get_substs(regtype="FF", regen="ON", regset=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG".format(iol), ["OFF", "ON"],
lambda x: get_substs(regtype="OUTREG", regen=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG.REGSET".format(iol), ["SET", "RESET"],
lambda x: get_substs(regtype="OUTREG", regen="ON", regset=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG.OUTREGMODE".format(iol), ["FF", "LATCH"],
lambda x: get_substs(regtype="OUTREG", regen="ON", regmode=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG".format(iol), ["OFF", "ON"],
lambda x: get_substs(regtype="TSREG", regen=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG.OUTREGMODE".format(iol), ["FF", "LATCH"],
lambda x: get_substs(regtype="TSREG", regen="ON", regmode=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG.REGSET".format(iol), ["SET", "RESET"],
lambda x: get_substs(regtype="TSREG", regen="ON", regset=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.SRMODE".format(iol), ["ASYNC", "LSR_OVER_CE"],
lambda x: get_substs(srmode=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.CEIMUX".format(iol), ["CEMUX", "1"],
lambda x: get_substs(ceimux=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.CEOMUX".format(iol), ["CEMUX", "1"],
lambda x: get_substs(ceomux=x), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.DATAMUX_OREG".format(iol), ["PADDO", "IOLDO"],
lambda x: get_substs(datamux=x), empty_bitfile, False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "slice.v"
def per_slice(slicen):
def get_substs(mode="LOGIC", kv=None):
if kv is None:
config = ""
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(z=slicen, mode=mode, config=config)
modes = ["LOGIC", "CCU2"]
if slicen in ("A", "B"):
modes.append("DPRAM")
if slicen == "C":
modes.append("RAMW")
nonrouting.fuzz_enum_setting(cfg, empty, "SLICE{}.MODE".format(slicen),
modes, lambda x: get_substs(x), False)
nonrouting.fuzz_enum_setting(
cfg, empty, "SLICE{}.CCU2.INJECT".format(slicen), ["YES", "NO"],
lambda x: get_substs("CCU2", ("INJECT", x)), False)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
pytrellis.load_database("../../../database")
for job in jobs:
cfg = job["cfg"]
side = job["side"]
pins = job["pins"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pio.v"
def per_pin(pin):
loc, pio = pin
def get_substs(iomode, extracfg=None):
if iomode == "NONE":
iodir, type = "NONE", ""
else:
iodir, type = iomode.split("_", 1)
substs = {
"dir": iodir,
"io_type": type,
"loc": loc,
"extra_attrs": "",
"cfg_vio": "3.3"
}
if extracfg is not None:
substs["extra_attrs"] = '(* {}="{}" *)'.format(extracfg[0], extracfg[1])
if side == "B":
substs["cfg_vio"] = get_cfg_vccio(type)
return substs
modes = ["NONE"]
for iodir in ("INPUT", "OUTPUT", "BIDIR"):
modes += [iodir + "_" + _ for _ in get_io_types(iodir, pio, side)]
nonrouting.fuzz_enum_setting(cfg, "PIO{}.BASE_TYPE".format(pio), modes,
lambda x: get_substs(iomode=x),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.PULLMODE".format(pio), ["UP", "DOWN", "NONE"],
lambda x: get_substs(iomode="INPUT_LVCMOS33", extracfg=("PULLMODE", x)),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.SLEWRATE".format(pio), ["FAST", "SLOW"],
lambda x: get_substs(iomode="OUTPUT_LVCMOS33", extracfg=("SLEWRATE", x)),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.DRIVE".format(pio), ["4", "8", "12", "16"],
lambda x: get_substs(iomode="OUTPUT_LVCMOS33", extracfg=("DRIVE", x)),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.HYSTERESIS".format(pio), ["ON", "OFF"],
lambda x: get_substs(iomode="INPUT_LVCMOS33", extracfg=("HYSTERESIS", x)),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.OPENDRAIN".format(pio), ["ON", "OFF"],
lambda x: get_substs(iomode="OUTPUT_LVCMOS33", extracfg=("OPENDRAIN", x)),
empty_bitfile)
if loc in ('T', 'B'):
nonrouting.fuzz_enum_setting(cfg, "PIO{}.CLAMP".format(pio), ["ON", "OFF"],
lambda x: get_substs(iomode="INPUT_LVCMOS33", extracfg=("CLAMP", x)),
empty_bitfile)
fuzzloops.parallel_foreach(pins, per_pin)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "reg.ncl"
def per_slice(slicen):
r = 0
def get_substs(regset="RESET", sd="0", lsrmode="LSR", gsr="DISABLED"):
return dict(slice=slicen, r=str(r), regset=regset, sd=sd, lsrmode=lsrmode, gsr=gsr)
for r in range(2):
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.REGSET".format(slicen, r), ["RESET", "SET"],
lambda x: get_substs(regset=x),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.SD".format(slicen, r), ["0", "1"],
lambda x: get_substs(sd=x),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.LSRMODE".format(slicen, r), ["LSR", "PRLD"],
lambda x: get_substs(lsrmode=x),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.GSR".format(slicen), ["DISABLED", "ENABLED"],
lambda x: get_substs(gsr=x),
empty_bitfile)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(mode="", settings={}, program={}, route=""):
if mode == "" or mode == "NONE":
delay = ""
else:
delay = ",".join(
["DELAY:::DEL_MODE={}".format(mode)] +
["{}={}".format(k, v) for k, v in settings.items()])
program = " ".join(
["{}:{}".format(k, v) for k, v in program.items()])
if side in ("T, B"):
s = "S"
else:
s = ""
if route != "":
route = "route\n\t\t{}_IOLDO{}.{}_IOLDO{}_PIO,\n\t\t{}_IOLDOD{}_{}IOLOGIC.{}_IOLDO{};".format(
rc, iol, rc, iol, rc, iol, s, rc, iol)
return dict(loc=loc,
delay=delay,
program=program,
route=route,
s=s)
cfg = job["cfg"]
loc = job["site"]
iol = job["iol"]
side = job["side"]
rc = job["rc"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "iologic.ncl"
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.DELAY.OUTDEL".format(iol), ["DISABLED", "ENABLED"],
lambda x: get_substs(route=(x if x != "DISABLED" else "")),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(
cfg, "IOLOGIC{}.DELAY.WAIT_FOR_EDGE".format(iol),
["DISABLED", "ENABLED"],
lambda x: get_substs(mode="USER_DEFINED",
settings={
"DEL_VALUE": 0,
"WAIT_FOR_EDGE": x
}), empty_bitfile, False)
nonrouting.fuzz_word_setting(
cfg, "IOLOGIC{}.DELAY.DEL_VALUE".format(iol), 7,
lambda x: get_substs(mode="USER_DEFINED",
settings={
"DEL_VALUE": todecstr(x),
"WAIT_FOR_EDGE": "DISABLED"
}), empty_bitfile)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("DLLDEL_CORE" in x or "JZ_I4" in x)
def pip_filter(x, nodes):
src, snk = x
return True
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, pip_predicate=pip_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
def per_cfg(x):
cfg = x["cfg"]
cfg.setup()
r, c = x["rc"]
cfg.sv = "../shared/empty_40.v"
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "dlldel.v"
site = "DLLDEL_CORE_R{}C{}".format(r, c)
dd = cfg.job[3:]
def get_substs(mode="DLLDEL_CORE", kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.MODE".format(dd), ["NONE", "DLLDEL_CORE"],
lambda x: get_substs(mode=x), False,
desc="DLLDEL primitive mode")
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.ENABLE".format(dd), ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("ENABLE", x)), False,
desc="DLLDEL primitive mode")
def intval(vec):
x = 0
for i, b in enumerate(vec):
if b:
x |= (1 << i)
return x
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.DEL_ADJUST".format(dd), ["PLUS", "MINUS"],
lambda x: get_substs(kv=("DEL_ADJUST", x)), False)
nonrouting.fuzz_word_setting(cfg, "DLLDEL{}.ADJUST".format(dd), 9,
lambda x: get_substs(kv=("ADJUST", str(intval(x)))))
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.CLKINMUX".format(dd), ["CLKIN", "INV"],
lambda x: get_substs(kv=("CLKIN", x), mux=True), False)
fuzzloops.parallel_foreach(configs, per_cfg)
def main():
cfg.setup()
cfg.sv = "ebr.v"
def per_word(w):
nonrouting.fuzz_ip_word_setting(
cfg, "INITVAL_{:02X}".format(w), 320,
lambda b: dict(a="{:02X}".format(w),
v="0x{:080x}".format(bin2dec(b))))
fuzzloops.parallel_foreach(range(0x40), per_word)
def main():
def per_config(config):
bank, site, cfg = config
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
if cfg.device == "LIFCL-17":
cfg.sv = "../031-io_mode/iob_17.v"
else:
cfg.sv = "../031-io_mode/iob_40.v"
def get_substs(iotype="LVCMOS18H", kv=None, vcc=None, diff=False, tmux="#SIG"):
if kv is not None:
extra_config = ",{}={}".format(kv[0], kv[1])
else:
extra_config = ""
if diff:
primtype = "DIFFIO18_CORE"
elif bank in (3, 4, 5):
primtype = "SEIO18_CORE"
else:
primtype = "SEIO33_CORE"
return dict(cmt="//" if iotype == "NONE" else "",
pintype="inout", primtype=primtype, site=site, iotype=iotype, t=tmux, extra_config=extra_config, vcc=vcc)
if bank in (3, 4, 5):
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.VCC".format(bank), ["NONE", "1V0", "1V2", "1V5", "1V8"],
lambda x: get_substs(iotype=vcc_to_io_18[x], vcc=x.replace("V", ".")), False,
assume_zero_base=True,
desc="VccIO of bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.DIFF_IO".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype=("SSTL15D_I" if x == "ON" else "SSTL15_I"), diff=(x == "ON"), vcc="1.5"), False,
desc="use differential IO in bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.REF_IO".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype=("SSTL15_I" if x == "ON" else "LVCMOS15H"), vcc="1.5"), False,
desc="use referenced inputs in bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.LVDS_IO".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype=("LVDS" if x == "ON" else "LVCMOS18H"), diff=True, vcc="1.8"), False,
desc="use LVDS IO in bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.SLVS_IO".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype=("SLVS" if x == "ON" else "HSUL12"), diff=(x == "ON"), vcc="1.2"), False,
desc="use SLVS IO in bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.MIPI_DPHY_IO".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype=("MIPI_DPHY" if x == "ON" else "HSUL12"), diff=(x == "ON"), vcc="1.2"), False,
desc="use DPHY IO in bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.VREF1_USED".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype="SSTL15_I", vcc="1.5", kv=("VREF", "VREF1_LOAD" if x == "ON" else "OFF")), False,
desc="use VREF1 input for bank {}".format(bank))
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.VREF2_USED".format(bank), ["OFF", "ON"],
lambda x: get_substs(iotype="SSTL15_I", vcc="1.5", kv=("VREF", "VREF2_LOAD" if x == "ON" else "OFF")), False,
desc="use VREF2 input for bank {}".format(bank))
else:
nonrouting.fuzz_enum_setting(cfg, empty, "BANK{}.VCC".format(bank), ["NONE", "1V2", "1V5", "1V8", "2V5", "3V3"],
lambda x: get_substs(iotype=vcc_to_io_33[x], vcc=x.replace("V", ".")), False,
assume_zero_base=True,
desc="VccIO of bank {}".format(bank))
fuzzloops.parallel_foreach(configs, per_config)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(settings, mode="MULT18X18D"):
if mode == "NONE":
comment = "//"
else:
comment = ""
return dict(loc=loc, mode=mode, settings=",".join(["{}={}".format(k, v) for k, v in settings.items()]),
comment=comment)
loc, mult, cfg = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "dspconfig.ncl"
nonrouting.fuzz_enum_setting(cfg, "{}.MODE".format(mult), ["NONE", "MULT18X18D"],
lambda x: get_substs(settings={}, mode=x), empty_bitfile, False)
regs = ["INPUTA", "INPUTB", "INPUTC", "PIPELINE", "OUTPUT"]
clks = ["NONE", "CLK0", "CLK1", "CLK2", "CLK3"]
cens = ["CE0", "CE1", "CE2", "CE3"]
rsts = ["RST0", "RST1", "RST2", "RST3"]
for reg in regs:
nonrouting.fuzz_enum_setting(cfg, "{}.REG_{}_CLK".format(mult, reg), clks,
lambda x: get_substs(settings={"REG_{}_CLK".format(reg): x}), empty_bitfile,
False)
nonrouting.fuzz_enum_setting(cfg, "{}.REG_{}_CE".format(mult, reg), cens,
lambda x: get_substs(settings={"REG_{}_CE".format(reg): x}), empty_bitfile,
False)
nonrouting.fuzz_enum_setting(cfg, "{}.REG_{}_RST".format(mult, reg), rsts,
lambda x: get_substs(settings={"REG_{}_RST".format(reg): x}), empty_bitfile,
False)
for clk in ["CLK0", "CLK1", "CLK2", "CLK3"]:
nonrouting.fuzz_enum_setting(cfg, "{}.{}_DIV".format(mult, clk), ["ENABLED", "DISABLED"],
lambda x: get_substs(settings={"{}_DIV".format(clk): x}), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.CAS_MATCH_REG".format(mult), ["FALSE", "TRUE"],
lambda x: get_substs(settings={"CAS_MATCH_REG": x}), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.MULT_BYPASS".format(mult), ["DISABLED", "ENABLED"],
lambda x: get_substs(settings={"MULT_BYPASS": x}), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(mult), ["DISABLED", "ENABLED"],
lambda x: get_substs(settings={"GSR": x}), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.RESETMODE".format(mult), ["SYNC", "ASYNC"],
lambda x: get_substs(settings={"RESETMODE": x}), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.SOURCEB_MODE".format(mult),
["B_SHIFT", "C_SHIFT", "B_C_DYNAMIC", "HIGHSPEED"],
lambda x: get_substs(settings={"SOURCEB_MODE": x}), empty_bitfile, False)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
cfg.setup()
cfg.sv = "lut.v"
def per_slice(slicen):
for k in range(2):
def get_substs(bits):
return dict(z=slicen, k=str(k), func=get_lut_function(bits))
nonrouting.fuzz_word_setting(cfg, "SLICE{}.K{}.INIT".format(slicen, k), 16, get_substs,
desc="SLICE {} LUT{} init value".format(slicen, k))
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "reg.ncl"
def per_slice(slicen):
r = 0
def get_substs(regset="RESET",
sd="0",
gsr="DISABLED",
regmode="FF",
clkmode="CLK"):
return dict(slice=slicen,
r=str(r),
regset=regset,
sd=sd,
gsr=gsr,
regmode=regmode,
clkmode=clkmode)
for r in range(2):
nonrouting.fuzz_enum_setting(
cfg, "SLICE{}.REG{}.REGSET".format(slicen,
r), ["RESET", "SET"],
lambda x: get_substs(regset=x), empty_bitfile)
nonrouting.fuzz_enum_setting(cfg,
"SLICE{}.REG{}.SD".format(slicen, r),
["0", "1"],
lambda x: get_substs(sd=x),
empty_bitfile)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.GSR".format(slicen),
["DISABLED", "ENABLED"],
lambda x: get_substs(gsr=x),
empty_bitfile)
# The below will be part of SLICE parameters in yosys models to
# decouple latches from registers. However, fuzz here b/c it makes
# sense.
# CLKMUX appears to be inverted when in latch mode...
# i.e. an inverted clock is a positive-level triggered latch.
#
# I cannot seem to isolate the REGMODE bit without setting the
# CLKMUX bit...
nonrouting.fuzz_enum_setting(
cfg, "SLICE{}.REGMODE".format(slicen), ["FF", "LATCH"],
lambda x: get_substs(regmode=x,
clkmode="CLK:::CLK=#INV"
if "LATCH" else "CLK"), empty_bitfile)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
pytrellis.load_database("../../../database")
for job in jobs:
cfg = job["cfg"]
side = job["side"]
pins = job["pins"]
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pio.v"
def per_pin(pin):
loc, pio = pin
def get_substs(iomode, extracfg=None):
if iomode == "NONE":
iodir, type = "NONE", ""
else:
iodir, type = iomode.split("_", 1)
substs = {
"dir": iodir,
"io_type": type,
"loc": loc,
"extra_attrs": "",
"cfg_vio": "3.3"
}
if extracfg is not None:
substs["extra_attrs"] = '(* {}="{}" *)'.format(extracfg[0], extracfg[1])
if side == "B":
substs["cfg_vio"] = get_cfg_vccio(type)
return substs
modes = ["NONE"]
nonrouting.fuzz_enum_setting(cfg, "PIO{}.TERMINATION_1V8".format(pio), ["OFF", "50", "75", "150"],
lambda x: get_substs(iomode="BIDIR_SSTL18_I", extracfg=("TERMINATION", x)),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.TERMINATION_1V5".format(pio), ["OFF", "50", "75", "150"],
lambda x: get_substs(iomode="BIDIR_SSTL15_I", extracfg=("TERMINATION", x)),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.TERMINATION_1V35".format(pio), ["OFF", "50", "75", "150"],
lambda x: get_substs(iomode="BIDIR_SSTL135_I", extracfg=("TERMINATION", x)),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "PIO{}.DIFFRESISTOR".format(pio), ["OFF", "100"],
lambda x: get_substs(iomode="INPUT_LVDS", extracfg=("DIFFRESISTOR", x)),
empty_bitfile, False)
fuzzloops.parallel_foreach(pins, per_pin)
def main():
def per_cib(cib):
rc, cfg = cib
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
r, c = rc
# CIB F/Q "used" bits
nodes = ["R{}C{}_JF{}".format(r, c, i) for i in range(8)]
nodes += ["R{}C{}_JQ{}".format(r, c, i) for i in range(8)]
node_data = lapie.get_node_data(cfg.udb, nodes)
for n in node_data:
to_wire = n.name
setting_name = to_wire.split("_")[1] + "_USED"
from_wire = None
for p in n.uphill_pips:
if "CIBTEST" not in p.from_wire:
from_wire = p.from_wire
break
assert from_wire is not None
arcs_attr = r', \dm:arcs ="{}.{}"'.format(to_wire, from_wire)
nonrouting.fuzz_enum_setting(
cfg, empty, "CIB." + setting_name, ["NO", "YES"],
lambda x: dict(arcs_attr=arcs_attr)
if x == "YES" else {}, False)
# CIBMUXIN -> CIBMUXOUT
cfg.sv = "cib_iomux_40.v"
for x in ("A", "B", "C", "D"):
# Stop Radiant trying to tie unused outputs; as this causes weird bit patterns
extra_arcs = []
for i in range(8):
for x2 in ("A", "B", "C", "D"):
if x2 == x:
continue
extra_arcs.append(
"R{r}C{c}_JCIBMUXOUT{x}{i}.R{r}C{c}_JCIBMUXINA{i}".
format(r=r, c=c, x=x2, i=i))
cibmuxout = [
"R{}C{}_JCIBMUXOUT{}{}".format(r, c, x, i) for i in range(8)
]
fuzz_interconnect(
config=cfg,
nodenames=cibmuxout,
regex=False,
bidir=False,
full_mux_style=True,
extra_substs=dict(extra_arc=" ".join(extra_arcs)))
fuzzloops.parallel_foreach(configs, per_cib)
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(mode="PCSCLKDIV", program=None):
if mode == "NONE":
comment = "//"
else:
comment = ""
if program is not None:
program = ":::" + ",".join(
["{}={}".format(k, v) for k, v in program.items()])
else:
program = ":#ON"
return dict(loc=loc, comment=comment, program=program)
cfg, loc, rc = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "pcsclkdiv.ncl"
nonrouting.fuzz_enum_setting(
cfg, "{}.MODE".format(loc), ["NONE", "PCSCLKDIV"],
lambda x: get_substs(mode=x, program={"GSR": "ENABLED"}),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(loc),
["DISABLED", "ENABLED"],
lambda x: get_substs(program={"GSR": x}),
empty_bitfile, False)
cfg.ncl = "pcsclkdiv_routing.ncl"
nets = [
"{}_JRST_{}".format(rc, loc),
"{}_JSEL2_{}".format(rc, loc),
"{}_JSEL1_{}".format(rc, loc),
"{}_JSEL0_{}".format(rc, loc),
"{}_CDIV1_{}".format(rc, loc),
"{}_CDIVX_{}".format(rc, loc),
"{}_CLKI_{}".format(rc, loc),
"{}_PCSCDIVI{}".format(rc, loc[-1]),
"{}_JPCSCDIVCIB{}".format(rc, loc[-1]),
]
interconnect.fuzz_interconnect_with_netnames(
cfg,
nets,
bidir=True,
)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "ccu2.ncl"
def per_slice(slicen):
def get_substs(ij1_0="YES", ij1_1="YES"):
return dict(slice=slicen, ij1_0=ij1_0, ij1_1=ij1_1)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.CCU2.INJECT1_0".format(slicen), ["YES", "NO"],
lambda x: get_substs(ij1_0=x),
empty_bitfile, True)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.CCU2.INJECT1_1".format(slicen), ["YES", "NO"],
lambda x: get_substs(ij1_1=x),
empty_bitfile, True)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main():
jobs = []
jobs += cell_fuzzers.timing_configs("picorv32",
"../../resource/picorv32_x20.v", "85")
def per_job(job):
grade, cfg = job
cfg.setup(skip_specimen=True)
bitf = cfg.build_design(cfg.ncl, {}, backanno=True, substitute=False)
ncl = bitf.replace(".bit", "_out.ncl")
sdf = bitf.replace(".bit", ".sdf")
data = timing_solver.solve_pip_delays(ncl, sdf)
db = timing_dbs.interconnect_db_path("ECP5", grade)
with open(db, "w") as f:
json.dump(data, f, indent=4, sort_keys=True)
fuzzloops.parallel_foreach(jobs, per_job)
def main():
pytrellis.load_database("../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "clkmux.ncl"
def per_clk(clkn):
def get_substs(clkmux):
if clkmux == "INV":
clkmux = "CLK:::CLK=#INV"
return dict(c=clkn, clkmux=clkmux)
nonrouting.fuzz_enum_setting(cfg, "CLK{}.CLKMUX".format(clkn),
["CLK", "INV"],
lambda x: get_substs(clkmux=x),
empty_bitfile, True)
fuzzloops.parallel_foreach(["0", "1"], per_clk)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "wremux.ncl"
def per_slice(slicen):
def get_substs(wremux):
if wremux == "INV":
wremux = "WRE:::WRE=#INV"
if wremux == "0":
wremux = "1:::1=0"
return dict(slice=slicen, wremux=wremux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.WREMUX".format(slicen), ["0", "1", "WRE", "INV"],
lambda x: get_substs(wremux=x),
empty_bitfile, False)
fuzzloops.parallel_foreach(["A"], per_slice)
def main():
pytrellis.load_database("../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "lut.ncl"
def per_slice(slicen):
for k in range(2):
def get_substs(bits):
return dict(slice=slicen,
k=str(k),
lut_func=get_lut_function(bits))
nonrouting.fuzz_word_setting(cfg,
"SLICE{}.K{}.INIT".format(slicen, k),
16, get_substs, empty_bitfile)
fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
