def test_all_glb_config_register():
global_buffer = GlobalBuffer(num_banks=32,
num_io=8,
num_cfg=8,
bank_addr_width=17,
glb_addr_width=32,
cfg_addr_width=32,
cfg_data_width=32,
axi_addr_width=12)
glb = Glb(global_buffer)
with tempfile.TemporaryDirectory() as tempdir:
filename = os.path.join(tempdir, "glb_config.json")
result = glb.dump_all_config()
with open(filename, "w+") as f:
json.dump(result, f)
def test_glb_bs_gen():
global_buffer = GlobalBuffer(num_banks=32,
num_io=8,
num_cfg=8,
bank_addr_width=17,
glb_addr_width=32,
cfg_addr_width=32,
cfg_data_width=32,
axi_addr_width=12)
glb = Glb(global_buffer)
dummy_collateral = (("in", 16), ("out", 16))
bitstream = glb.config(dummy_collateral)
with tempfile.TemporaryDirectory() as tempdir:
filename = os.path.join(tempdir, "glb_bs.bs")
with open(filename, "w+") as f:
bs = [
"{0:03X} {1:08X}".format(entry[0], entry[1])
for entry in bitstream
]
f.write("\n".join(bs))
def __init__(self,
width,
height,
add_pd,
interconnect_only: bool = False,
use_sram_stub: bool = True,
standalone: bool = False):
super().__init__()
# Check consistency of @standalone and @interconnect_only parameters. If
# @standalone is True, then interconnect_only must also be True.
if standalone:
assert interconnect_only
# configuration parameters
config_addr_width = 32
config_data_width = 32
self.config_addr_width = config_addr_width
self.config_data_width = config_data_width
axi_addr_width = 13
glb_axi_addr_width = 12
axi_data_width = 32
# axi_data_width must be same as cgra config_data_width
assert axi_data_width == config_data_width
tile_id_width = 16
config_addr_reg_width = 8
num_tracks = 5
# size
self.width = width
self.height = height
# only north side has IO
if standalone:
io_side = IOSide.None_
else:
io_side = IOSide.North
if not interconnect_only:
# global buffer parameters
# width must be even number
assert (self.width % 2) == 0
num_glb_tiles = self.width // 2
bank_addr_width = 17
bank_data_width = 64
banks_per_tile = 2
glb_addr_width = (bank_addr_width +
magma.bitutils.clog2(banks_per_tile) +
magma.bitutils.clog2(num_glb_tiles))
# bank_data_width must be the size of bitstream
assert bank_data_width == config_addr_width + config_data_width
wiring = GlobalSignalWiring.ParallelMeso
self.global_controller = GlobalController(
addr_width=config_addr_width,
data_width=config_data_width,
axi_addr_width=axi_addr_width,
axi_data_width=axi_data_width,
num_glb_tiles=num_glb_tiles,
glb_addr_width=glb_addr_width,
block_axi_addr_width=glb_axi_addr_width)
self.global_buffer = GlobalBuffer(
num_glb_tiles=num_glb_tiles,
num_cgra_cols=width,
bank_addr_width=bank_addr_width,
bank_data_width=bank_data_width,
cfg_addr_width=config_addr_width,
cfg_data_width=config_data_width,
axi_addr_width=glb_axi_addr_width,
axi_data_width=axi_data_width)
else:
wiring = GlobalSignalWiring.Meso
interconnect = create_cgra(width,
height,
io_side,
reg_addr_width=config_addr_reg_width,
config_data_width=config_data_width,
tile_id_width=tile_id_width,
num_tracks=num_tracks,
add_pd=add_pd,
use_sram_stub=use_sram_stub,
global_signal_wiring=wiring,
mem_ratio=(1, 4),
standalone=standalone)
self.interconnect = interconnect
if not interconnect_only:
self.add_ports(
jtag=JTAGType,
clk_in=magma.In(magma.Clock),
reset_in=magma.In(magma.AsyncReset),
proc_packet=ProcPacketIfc(glb_addr_width,
bank_data_width).slave,
axi4_slave=AXI4LiteIfc(axi_addr_width, axi_data_width).slave,
interrupt=magma.Out(magma.Bit),
cgra_running_clk_out=magma.Out(magma.Clock),
)
# top <-> global controller ports connection
self.wire(self.ports.clk_in, self.global_controller.ports.clk_in)
self.wire(self.ports.reset_in,
self.global_controller.ports.reset_in)
self.wire(self.ports.jtag, self.global_controller.ports.jtag)
self.wire(self.ports.axi4_slave,
self.global_controller.ports.axi4_slave)
self.wire(self.ports.interrupt,
self.global_controller.ports.interrupt)
self.wire(self.ports.cgra_running_clk_out,
self.global_controller.ports.clk_out)
# top <-> global buffer ports connection
self.wire(self.ports.proc_packet,
self.global_buffer.ports.proc_packet)
glb_glc_wiring(self)
glb_interconnect_wiring(self)
glc_interconnect_wiring(self)
else:
# lift all the interconnect ports up
for name in self.interconnect.interface():
self.add_port(name, self.interconnect.ports[name].type())
self.wire(self.ports[name], self.interconnect.ports[name])
self.add_ports(
clk=magma.In(magma.Clock),
reset=magma.In(magma.AsyncReset),
config=magma.In(
ConfigurationType(self.interconnect.config_data_width,
self.interconnect.config_data_width)),
stall=magma.In(
magma.Bits[self.interconnect.stall_signal_width]),
read_config_data=magma.Out(magma.Bits[config_data_width]))
self.wire(self.ports.clk, self.interconnect.ports.clk)
self.wire(self.ports.reset, self.interconnect.ports.reset)
self.wire(self.ports.config, self.interconnect.ports.config)
self.wire(self.ports.stall, self.interconnect.ports.stall)
self.wire(self.interconnect.ports.read_config_data,
self.ports.read_config_data)
def __init__(self,
width,
height,
add_pd,
interconnect_only: bool = False,
use_sram_stub: bool = True):
super().__init__()
# configuration parameters
config_addr_width = 32
config_data_width = 32
axi_addr_width = 12
tile_id_width = 16
config_addr_reg_width = 8
num_tracks = 5
# size
self.width = width
self.height = height
# only north side has IO
io_side = IOSide.North
# global buffer parameters
num_banks = 32
bank_addr_width = 17
bank_data_width = 64
glb_addr_width = 32
# parallel configuration parameter
num_parallel_cfg = math.ceil(width / 4)
# number of input/output channels parameter
num_io = math.ceil(width / 4)
if not interconnect_only:
wiring = GlobalSignalWiring.ParallelMeso
self.global_controller = GlobalController(config_addr_width,
config_data_width,
axi_addr_width)
self.global_buffer = GlobalBuffer(num_banks=num_banks,
num_io=num_io,
num_cfg=num_parallel_cfg,
bank_addr_width=bank_addr_width,
glb_addr_width=glb_addr_width,
cfg_addr_width=config_addr_width,
cfg_data_width=config_data_width,
axi_addr_width=axi_addr_width)
else:
wiring = GlobalSignalWiring.Meso
interconnect = create_cgra(width,
height,
io_side,
reg_addr_width=config_addr_reg_width,
config_data_width=config_data_width,
tile_id_width=tile_id_width,
num_tracks=num_tracks,
add_pd=add_pd,
use_sram_stub=use_sram_stub,
global_signal_wiring=wiring,
num_parallel_config=num_parallel_cfg,
mem_ratio=(1, 4))
self.interconnect = interconnect
if not interconnect_only:
self.add_ports(
jtag=JTAGType,
clk_in=magma.In(magma.Clock),
reset_in=magma.In(magma.AsyncReset),
soc_data=SoCDataType(glb_addr_width, bank_data_width),
axi4_ctrl=AXI4SlaveType(axi_addr_width, config_data_width),
cgra_running_clk_out=magma.Out(magma.Clock),
)
# top <-> global controller ports connection
self.wire(self.ports.clk_in, self.global_controller.ports.clk_in)
self.wire(self.ports.reset_in,
self.global_controller.ports.reset_in)
self.wire(self.ports.jtag, self.global_controller.ports.jtag)
self.wire(self.ports.axi4_ctrl,
self.global_controller.ports.axi4_ctrl)
self.wire(self.ports.cgra_running_clk_out,
self.global_controller.ports.clk_out)
# top <-> global buffer ports connection
self.wire(self.ports.soc_data, self.global_buffer.ports.soc_data)
glc_interconnect_wiring(self)
glb_glc_wiring(self)
glb_interconnect_wiring(self, width, num_parallel_cfg)
else:
# lift all the interconnect ports up
self._lift_interconnect_ports(config_data_width)
self.mapper_initalized = False
self.__rewrite_rules = None
def test_compile():
global_buffer = GlobalBuffer(16, 32)
global_buffer_circ = global_buffer.circuit()
magma.compile("global_buffer", global_buffer_circ, output="coreir-verilog")