def simpleTest():
globs.init()
globs.load_params()
globs.params.vprVersion = 7
nets = parseRouting('route.r.vpr7')
for net in nets:
print '\n ------ net ---------'
print net.name
print net.source
print net.sinks
for trace in net.trace:
print '\n --- trace ---'
print trace.type
print trace.loc
print trace.index
#now vpr8
print '\n----------now vpr8----------------\n'
globs.params.vprVersion = 8
nets = parseRouting('route.r.vpr8')
for net in nets:
print '\n ------ net ---------'
print net.name
print net.source
print net.sinks
for trace in net.trace:
print '\n --- trace ---'
print trace.type
print trace.loc
print trace.index
def simpleTest():
globs.init()
globs.load_params()
clusters = parseNetlist('netlistTest.net')
for cluster in clusters:
print 'cluster: ' + cluster.name
for input in cluster.inputs:
print 'cluster input: ' + input
bleCount = 1
for ble in cluster.bles:
print 'analyse ble ' + str(bleCount)
for (name, number) in ble.inputs:
print 'ble input: ' + name + ' ' + str(number)
if (ble.lut is None):
print 'no lut'
else:
print 'has lut: ' + ble.lut.name
if (ble.flipflop is None):
print 'no flipflop'
else:
print 'has flipflop: ' + ble.flipflop.name
bleCount = bleCount + 1
print 'end test'
print 'vpr8 test'
clusters = parseNetlist('netlist.net.vpr8')
for cluster in clusters:
print 'cluster: ' + cluster.name
for input in cluster.inputs:
print 'cluster input: ' + input
bleCount = 1
for ble in cluster.bles:
print 'analyse ble ' + str(bleCount)
for (name, number) in ble.inputs:
print 'ble input: ' + name + ' ' + str(number)
if (ble.lut is None):
print 'no lut'
else:
print 'has lut: ' + ble.lut.name
if (ble.flipflop is None):
print 'no flipflop'
else:
print 'has flipflop: ' + ble.flipflop.name
bleCount = bleCount + 1
print 'end test'
def TestParser():
globs.init()
globs.load_params()
globs.params.sdfUsedTool = "ise"
globs.params.sdfInterconnectCellType = "zuma_wrapper"
# cells = ParseSdf('Timing.sdf')
#
# for name,cell in cells.items():
#
# print "new cell: " + str(cell.instanceName) + "\n"
#
# for portName,port in cell.ports.items():
#
# print "new port: " + str(port.name)
# print "risingDelay: " + str(port.risingDelay)
# print "fallingDelay: " + str(port.fallingDelay)
#
# for pathName,ioPath in cell.ioPaths.items():
#
# print "new iopath: " + str(ioPath.name)
# print "risingDelay: " + str(ioPath.risingDelay)
# print "fallingDelay: " + str(ioPath.fallingDelay)
#
# print "\n"
globs.params.sdfUsedTool = "vivado"
cells = ParseSdf('postRoute.sdf')
for name,cell in cells.items():
print "new cell: " + str(cell.instanceName) + "\n"
for portName,port in cell.ports.items():
print "new port: " + str(port.name)
print "risingDelay: " + str(port.risingDelay)
print "fallingDelay: " + str(port.fallingDelay)
for pathName,ioPath in cell.ioPaths.items():
print "new iopath: " + str(ioPath.name)
print "risingDelay: " + str(ioPath.risingDelay)
print "fallingDelay: " + str(ioPath.fallingDelay)
for (input,clock),setupHold in cell.setupHolds.items():
print "new setuphold: " + str(setupHold.input) + ',' + str(setupHold.clock)
print "setupDelay: " + str(setupHold.setupDelay)
print "holdDelay: " + str(setupHold.holdDelay)
print "\n"
def simpleTest():
globs.init()
globs.load_params()
blocks = parsePlacement('place.p.vpr7')
for block in blocks:
print block.location
print block.name
print 'now vpr8'
blocks = parsePlacement('place.p.vpr8')
for block in blocks:
print block.location
print block.name
def bitToBlif(graph_file, verilog_file, blif_file, place_file, route_file,
net_file, mif_file, maxInputNum, useClock, useReset):
globs.init()
globs.load_params()
globs.clock = useClock
globs.reset = useReset
globs.maxInputNum = maxInputNum
#signal reverse build
globs.bit_to_blif = True
#Import graph from VTR
InitFpga.load_graph(graph_file)
#Build ZUMA verilog global routing
BuildVerilog.build_global_routing_verilog(verilog_file)
ParseBitstream.parseBitstream(mif_file)
Dump.dumpGraph('revereseGraph')
#output a BLIF of the design
OutputBlif.output_blif(blif_file)
def simpleTest():
globs.init()
globs.load_params()
globs.params.vprVersion = 7
blif = parseBlif('abc_out.blif')
print "\ninputs \n"
for input in blif.inputs:
print str(input.blifName) + " " + str(input.ioIndex) + "\n"
print "\noutputs \n"
for output in blif.outputs:
print str(output.blifName) + " " + str(output.ioIndex) + "\n"
print "\n latchces \n"
for latch in blif.latches:
print str(latch.inputNet) + " " + str(latch.outputNet) + "\n"
print "\n names \n"
for name in blif.names:
print str(name.inputNets) + " " + str(name.outputNet) + "\n"
print str(name.content)
mif_file = val
if id == '-blif_out_file':
blif_out_file = val
if id == '-use_reset':
if val == 'True':
globs.reset = True
if id == '-use_clock':
if val == 'True':
globs.clock = True
if id == '-used_inputs_number':
globs.maxInputNum = (int(val)-1)
globs.load_params()
#signal reverse build
globs.bit_to_blif = True
#Import graph from VTR
InitFpga.load_graph(graph_file)
#Build ZUMA verilog global routing
BuildVerilog.build_global_routing_verilog(verilog_file)
ParseBitstream.parseBitstream(mif_file)
Dump.dumpGraph('revereseGraph')
#output a BLIF of the design
OutputBlif.output_blif(blif_file)
verilog_file = val
if id == '-blif_file':
blif_file = val
if id == '-place_file':
place_file = val
if id == '-net_file':
net_file = val
if id == '-route_file':
route_file = val
if id == '-bit_file':
build_bit = True
bit_file = val
if id == '-blif_out_file':
blif_out_file = val
globs.load_params()
#Import graph from VTR
InitFpga.load_graph(graph_file)
#Build ZUMA verilog global routing
BuildVerilog.build_global_routing_verilog(verilog_file)
if build_bit:
#Read all VPR output files
ReadBlif.read_BLIF(blif_file)
ReadPlacement.read_placement(place_file)
ReadRouting.read_routing(route_file)
ReadNetlist.read_netlist(net_file)
def Zuma(verilog_file, graph_file, blif_file, place_file, net_file, route_file,
bit_file, blif_out_file, build_bit):
globs.init()
globs.load_params()
#Import graph from VTR
InitFpga.load_graph(graph_file)
#Build ZUMA verilog global routing
BuildVerilog.build_global_routing_verilog(verilog_file)
#dump the node graph. textual and graphical
if globs.params.dumpNodeGraph:
Dump.dumpGraph('unconfiguredGraph')
if build_bit:
#Read all VPR output files
ReadBlif.read_BLIF(blif_file)
ReadPlacement.read_placement(place_file)
ReadRouting.read_routing(route_file)
ReadNetlist.read_netlist(net_file)
#Build the bitstream
BuildBitstream.build_bitstream(bit_file)
buildPackedOverlay.createDefGenerated()
#dump the node graph. textual and graphical
if globs.params.dumpNodeGraph:
Dump.dumpGraph('configuredGraph')
if globs.params.dumpNodeGraph:
Dump.dumpTechnologyGraph('mappedGraph')
#output a BLIF of the design
OutputBlif.output_blif(blif_out_file)
#build a packed overlay
if globs.params.packedOverlay:
buildPackedOverlay.buildVerificationOverlay(
"packedOverlay.v", False, False)
if globs.params.blackBox:
buildPackedOverlay.buildVerificationOverlay(
"packedOverlayBlackBox.v", False, True)
#output a verification verilog file
if globs.params.verifyOverlay:
buildPackedOverlay.buildVerificationOverlay(
"verificationOverlay.v", True, False)
#dump a list of unconfigured nodes with their corresponding verilog names
if globs.params.dumpUnconfiguredNodes:
Dump.dumpUnconfiguredNodesToFile('unconfigured.txt')
#if we want to parse the sdf file
if globs.params.sdf:
ReadSDF.ReadSDF()
TimingAnalysisSDF.performTimingAnalysis()
if globs.params.vprAnnotation:
NodeGraphTiming.AnnotateTiming()
TimingAnnotation.annotateClusterTiming()
TimingAnnotation.annotateBack()
if globs.params.dumpNodeGraph:
Dump.dumpTechnologyGraph('mappedTimedGraph')
Dump.dumpGraph('timedGraph')
