Esempio n. 1
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    def test_read_config(self) -> None:
        """
        Test that reading it from config works.
        """
        src = """
vlsi.inputs.clocks:
- name: "my_port"
  period: "50 ns"
  path: "Top/clock"
  uncertainty: "1 ns"
  generated: true
  source_path: "Top/pll/out"
  divisor: 2
  group: "ClkGrp"
        """
        self.check_src(
            src,
            ClockPort(name="my_port",
                      period=TimeValue("50 ns"),
                      path="Top/clock",
                      uncertainty=TimeValue("1 ns"),
                      generated=True,
                      source_path="Top/pll/out",
                      divisor=2,
                      group="ClkGrp"))
Esempio n. 2
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    def test_round_trip(self) -> None:
        """
        Test that converting to and from dict works.
        """
        orig = DelayConstraint(name="mypin",
                               clock="clock",
                               direction="input",
                               delay=TimeValue("20 ns"))
        copied = DelayConstraint.from_dict(orig.to_dict())
        self.assertEqual(orig, copied)

        orig = DelayConstraint(name="pin_2",
                               clock="clock_20MHz",
                               direction="output",
                               delay=TimeValue("0.3 ns"))
        copied = DelayConstraint.from_dict(orig.to_dict())
        self.assertEqual(orig, copied)
Esempio n. 3
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    def test_optional_generated(self) -> None:
        """
        Test that the generated attribute is optional and that there is
        no effect if it is false.
        """
        src = """
vlsi.inputs.clocks:
- name: "my_port"
  period: "50 ns"
  path: "Top/clock"
  uncertainty: "1 ns"
  source_path: "Top/pll/out"
  divisor: 2
        """
        self.check_src(
            src,
            ClockPort(name="my_port",
                      period=TimeValue("50 ns"),
                      path="Top/clock",
                      uncertainty=TimeValue("1 ns"),
                      generated=None,
                      source_path=None,
                      divisor=None,
                      group=None))
        src2 = """
vlsi.inputs.clocks:
- name: "my_port"
  period: "50 ns"
  path: "Top/clock"
  uncertainty: "1 ns"
  generated: false
  source_path: "Top/pll/out"
  divisor: 2
        """
        self.check_src(
            src2,
            ClockPort(name="my_port",
                      period=TimeValue("50 ns"),
                      path="Top/clock",
                      uncertainty=TimeValue("1 ns"),
                      generated=False,
                      source_path=None,
                      divisor=None,
                      group=None))
Esempio n. 4
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    def test_invalid_direction(self) -> None:
        """
        Test that invalid directions are caught properly.
        """
        with self.assertRaises(ValueError):
            DelayConstraint(
                name="mypin",
                clock="clock",
                direction="bad",
                delay=TimeValue("20 ns")
            )

        with self.assertRaises(ValueError):
            DelayConstraint(
                name="mypin",
                clock="clock",
                direction="inputt",
                delay=TimeValue("20 ns")
            )

        with self.assertRaises(ValueError):
            DelayConstraint(
                name="mypin",
                clock="clock",
                direction="inputoutput",
                delay=TimeValue("20 ns")
            )

        with self.assertRaises(ValueError):
            DelayConstraint(
                name="mypin",
                clock="clock",
                direction="",
                delay=TimeValue("20 ns")
            )

        # Test that the error is raised with the dict as well.
        with self.assertRaises(ValueError):
            DelayConstraint.from_dict({
                "name": "mypin",
                "clock": "clock",
                "direction": "",
                "delay": "20 ns"
            })