def get(
cls,
clk,
rst,
state_var,
initial,
edge="rise",
lvl=1,
instance_name=None,
_signal_scope=None,
):
"""Get sequential block."""
seq = ClockedBlock.get(clk, edge)
const = []
rst_if = HDLIfElse(rst == lvl, tag="rst_if")
seq.add(rst_if)
# add cases
states = cls._collect_states()
cases = []
state_mapping = OrderedDict()
fsm = cls._infer_fsm(_signal_scope, states, initial, instance_name,
state_var)
# set state variable size
state_var.set_size(int(math.ceil(math.log2(float(len(states))))))
# add switch
sw = HDLSwitch(state_var)
rst_if.add_to_else_scope(sw)
i = 0
for state, (method, inputs) in states.items():
state_mapping[state] = i
case = HDLCase(HDLMacroValue(state),
tag="__autogen_case_{}".format(state))
case.add_to_scope(
HDLComment(
"case {}".format(state),
tag="__autogen_case_{}".format(state),
))
cases.append(case)
sw.add_case(case)
const.append(HDLMacro(state, i))
i += 1
if initial in state_mapping:
rst_if.add_to_if_scope(
HDLAssignment(state_var, HDLMacroValue(initial)))
else:
raise RuntimeError("initial state not specified")
# PROCESS STATES
return (seq, const, fsm)
def test_ifelse():
"""Test if-else."""
# create an if-else block
gen = VerilogCodeGenerator()
sig = HDLSignal(sig_type="comb", sig_name="test", size=1)
test_sig = HDLSignal(sig_type="reg", sig_name="counter", size=2)
assign_rhs = HDLExpression(test_sig) + 1
assignment = HDLAssignment(signal=test_sig, value=assign_rhs)
ifelse = HDLIfElse(condition=sig)
ifelse.add_to_if_scope(assignment)
# make else
assignment = HDLAssignment(signal=test_sig, value=0)
ifelse.add_to_else_scope(assignment)
print(gen.dump_element(ifelse))
def test_always():
"""Test always block."""
gen = VerilogCodeGenerator()
sig = HDLSignal(sig_type="reg", sig_name="clk", size=1)
sens = HDLSensitivityDescriptor(sens_type="rise", sig=sig)
sens_list = HDLSensitivityList()
sens_list.add(sens)
test_sig = HDLSignal(sig_type="reg", sig_name="counter", size=2)
rst_assign = HDLAssignment(signal=test_sig, value=0)
norm_expr = HDLExpression(test_sig) + 1
norm_assign = HDLAssignment(signal=test_sig, value=norm_expr)
rst = HDLSignal(sig_type="reg", sig_name="rst", size=1)
ifelse = HDLIfElse(condition=rst)
ifelse.add_to_if_scope(rst_assign)
ifelse.add_to_else_scope(norm_assign)
seq = HDLSequentialBlock(sensitivity_list=sens_list)
seq.add(ifelse)
print(gen.dump_element(seq))