def _impl(self):
DW = int(self.DATA_WIDTH)
polyBits, PW = self.parsePoly(self.POLY, self.POLY_WIDTH)
# xorMatrix = buildCrcMatrix_dataMatrix(polyCoefs, PW, DW)
# initXorMatrix = buildCrcMatrix_reg0Matrix(polyCoefs, PW, DW)
XOROUT = int(self.XOROUT)
_INIT = int(self.INIT)
initBits = [hBit(selectBit(_INIT, i)) for i in range(PW)]
finBits = [hBit(selectBit(XOROUT, i)) for i in range(PW)]
# rename to have shorter code
_inD = self._sig("d", self.dataIn._dtype)
_inD(self.dataIn)
inBits = list(iterBits(_inD))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
outBits = iterBits(self.dataOut)
crcMatrix = self.buildCrcXorMatrix(DW, polyBits)
res = self.applyCrcXorMatrix(crcMatrix, inBits, initBits,
bool(self.REFIN))
if self.REFOUT:
res = list(reversed(res))
finBits = reversedBitsInBytes(finBits)
for ob, b, fb in zip(outBits, res, finBits):
ob(b ^ fb)
def _impl(self):
DW = int(self.DATA_WIDTH)
polyBits, PW = self.parsePoly(self.POLY, self.POLY_WIDTH)
# xorMatrix = buildCrcMatrix_dataMatrix(polyCoefs, PW, DW)
# initXorMatrix = buildCrcMatrix_reg0Matrix(polyCoefs, PW, DW)
XOROUT = int(self.XOROUT)
_INIT = int(self.INIT)
initBits = [hBit(selectBit(_INIT, i))
for i in range(PW)]
finBits = [hBit(selectBit(XOROUT, i))
for i in range(PW)]
# rename to have shorter code
_inD = self._sig("d", self.dataIn._dtype)
_inD(self.dataIn)
inBits = list(iterBits(_inD))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
outBits = iterBits(self.dataOut)
crcMatrix = self.buildCrcXorMatrix(DW, polyBits)
res = self.applyCrcXorMatrix(
crcMatrix, inBits,
initBits, bool(self.REFIN))
if self.REFOUT:
res = list(reversed(res))
finBits = reversedBitsInBytes(finBits)
for ob, b, fb in zip(outBits, res, finBits):
ob(b ^ fb)
def _getitem__val_int(self, key):
updateTime = max(self.updateTime, key.updateTime)
keyVld = key._isFullVld()
if keyVld:
val = selectBit(self.val, key.val)
vld = selectBit(self.vldMask, key.val)
else:
val = 0
vld = 0
return self.__class__(val, BIT, vld, updateTime=updateTime)
def test_7bitAddr(self):
u = self.u
addr = 13
mode = 1
u.cntrl._ag.data.extend([
(START, 0),
] + [(WRITE, selectBit(addr, 7 - i - 1))
for i in range(7)] + [(WRITE, mode), (READ, 0), (NOP, 0)])
u.clk_cnt_initVal._ag.data.append(4)
self.runSim(700 * Time.ns)
self.assertValSequenceEqual(
u.i2c._ag.bits,
[I2cAgent.START] + [selectBit(addr, 7 - i - 1)
for i in range(7)] + [mode, 1])
def test_7bitAddr(self):
u = self.u
addr = 13
mode = 1
u.cntrl._ag.data.extend(
[(START, 0), ] +
[(WRITE, selectBit(addr, 7 - i - 1)) for i in range(7)] +
[(WRITE, mode),
(READ, 0),
(NOP, 0)
])
u.clk_cnt_initVal._ag.data.append(4)
self.runSim(700 * Time.ns)
self.assertValSequenceEqual(u.i2c._ag.bits,
[I2cAgent.START] +
[selectBit(addr, 7 - i - 1) for i in range(7)] +
[mode, 1])
def addValues(unit, data):
for d in data:
# because there are 4 bits
for i in range(4):
databit = getattr(unit, "a%d" % i)
if d is None:
dataBitval = None
else:
dataBitval = selectBit(d, i)
databit._ag.data.append(dataBitval)
def sendStr(self, string):
START_BIT = 0
STOP_BIT = 1
rx = self.u.rxd._ag.data
os = self.FREQ // self.BAUD
for ch in string:
rx.extend([START_BIT for _ in range(os)])
for i in range(8):
d = selectBit(ord(ch), i)
rx.extend([d for _ in range(os)])
rx.extend([STOP_BIT for _ in range(os)])
def _getitem__val(self, key):
updateTime = max(self.updateTime, key.updateTime)
keyVld = key._isFullVld()
val = 0
vld = 0
if isinstance(key._dtype, Integer):
if keyVld:
val = selectBit(self.val, key.val)
vld = selectBit(self.vldMask, key.val)
return BitsVal(val, BIT, vld, updateTime=updateTime)
elif key._dtype == SLICE:
if keyVld:
firstBitNo = key.val[1].val
size = key._size()
val = selectBitRange(self.val, firstBitNo, size)
vld = selectBitRange(self.vldMask, firstBitNo, size)
retT = vecT(size, signed=self._dtype.signed)
return BitsVal(val, retT, vld, updateTime=updateTime)
else:
raise TypeError(key)
def sendStr(self, string):
START_BIT = 0
STOP_BIT = 1
rx = self.u.rxd._ag.data
os = self.FREQ // self.BAUD
for ch in string:
rx.extend([START_BIT for _ in range(os)])
for i in range(8):
d = selectBit(ord(ch), i)
rx.extend([d for _ in range(os)])
rx.extend([STOP_BIT for _ in range(os)])
def _impl(self):
accumulator = self._reg("accumulator",
Bits(self.POLY_WIDTH),
defVal=self.INIT)
POLY = int(self.POLY)
xorBits = []
for i, b in enumerate(iterBits(accumulator)):
if selectBit(POLY, i):
xorBits.append(b)
assert xorBits
nextBit = Xor(*xorBits)
accumulator(Concat(accumulator[self.POLY_WIDTH - 1:], nextBit))
self.dataOut(accumulator[0])
def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i))
for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c",
Bits(self.POLY_WIDTH),
self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(
crcMatrix, inBits,
stateBits, bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext)))
)
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb
for rb, fb in zip(iterBits(state), finBits)]
)
)
else:
self.dataOut(state ^ Concat(*finBits))
def parsePoly(POLY, POLY_WIDTH) -> List[int]:
"""
:return: list of bits from polynome, extra MSB 1 is added
len of this list is POLY_WIDTH + 1
"""
PW = int(POLY_WIDTH)
poly = int(POLY) # [TODO] poly in str
if isinstance(poly, str):
polyCoefs = parsePolyStr(poly, PW)
elif isinstance(poly, int):
polyCoefs = [selectBit(poly, i) for i in range(PW)]
else:
raise NotImplementedError()
# LSB is usuaaly 1
return polyCoefs, PW
def parsePoly(POLY, POLY_WIDTH) -> List[int]:
"""
:return: list of bits from polynome, extra MSB 1 is added
len of this list is POLY_WIDTH + 1
"""
PW = int(POLY_WIDTH)
poly = int(POLY) # [TODO] poly in str
if isinstance(poly, str):
polyCoefs = parsePolyStr(poly, PW)
elif isinstance(poly, int):
polyCoefs = [selectBit(poly, i)
for i in range(PW)]
else:
raise NotImplementedError()
# LSB is usuaaly 1
return polyCoefs, PW
def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i)) for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c", Bits(self.POLY_WIDTH), self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(crcMatrix, inBits, stateBits,
bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(
self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext))))
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb for rb, fb in zip(iterBits(state), finBits)]))
else:
self.dataOut(state ^ Concat(*finBits))
def asciiArtOfChar(ch, inverted=True):
ch = ord(ch)
imgBuf = []
for y in range(8):
row = getCharRow(ch, y)
lineBuf = []
for x in range(8):
pix = selectBit(row, 8 - x - 1)
if inverted:
pix = not pix
if pix:
pix = ' '
else:
pix = '#'
lineBuf.append(pix)
imgBuf.append("".join(lineBuf))
lineBuf.clear()
return "\n".join(imgBuf)
def applyRequests(ram, requests):
"""
request has to be tuple (WRITE, addr, data) or (READ, addr)
data can be only 0 or 1 (because width of data port is 1)
"""
for req in requests:
m = req[0]
if m == WRITE:
data = req[2]
assert data == 1 or data == 0
ram.d._ag.data.append(data)
ram.we._ag.data.append(1)
elif m == READ:
ram.we._ag.data.append(0)
else:
raise Exception("invalid mode %s" % (repr(req[0])))
addr = req[1]
# ram addr has 6 bits
for i in range(6):
addrbit = getattr(ram, "a%d" % i)
addrBitval = selectBit(addr, i)
addrbit._ag.data.append(addrBitval)
def applyRequests(ram, requests):
"""
request has to be tuple (WRITE, addr, data) or (READ, addr)
data can be only 0 or 1 (because width of data port is 1)
"""
for req in requests:
m = req[0]
if m == WRITE:
data = req[2]
assert data == 1 or data == 0
ram.d._ag.data.append(data)
ram.we._ag.data.append(1)
elif m == READ:
ram.we._ag.data.append(0)
else:
raise Exception("invalid mode %s" % (repr(req[0])))
addr = req[1]
# ram addr has 6 bits
for i in range(6):
addrbit = getattr(ram, "a%d" % i)
addrBitval = selectBit(addr, i)
addrbit._ag.data.append(addrBitval)
def splitBits(self, v):
return deque([selectBit(v, i) for i in range(self.BITS_IN_WORD - 1, -1, -1)])
def test_parsePolyStr(self):
crc32_str = "x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1"
poly = parsePolyStr(crc32_str, 32)
expected = [selectBit(CRC_32.POLY, i) for i in range(CRC_32.WIDTH)]
self.assertEqual(poly, expected)
def crcToBf(crc):
return [selectBit(crc.POLY, i) for i in range(crc.WIDTH)]
def reverseBits(val, width):
v = 0
for i in range(width):
v |= (selectBit(val, width - i - 1) << i)
return v
def test_crc32_py(self):
self.assertEqual(crc32(b"aa"), crc32(b"a", crc32(b"a")))
# ! self.assertEqual(crc32(b"abcdefgh"), crc32(b"abcd", crc32(b"efgh")))
self.assertEqual(crc32(b"abcdefgh"), crc32(b"efgh", crc32(b"abcd")))
# ! self.assertEqual(crc32(b"abcdefgh"), crc32(b"efgh") ^ crc32(b"abcd"))
self.assertEqual(crc_hqx(b"aa", 0), crc_hqx(b"a", crc_hqx(b"a", 0)))
# ! self.assertEqual(crc_hqx(b"abcdefgh", 0), crc_hqx(b"abcd", crc_hqx(b"efgh", 0)))
self.assertEqual(crc_hqx(b"abcdefgh", 0),
crc_hqx(b"efgh", crc_hqx(b"abcd", 0)))
# ! self.assertEqual(crc_hqx(b"abcdefgh", 0), crc_hqx(b"efgh", 0) ^ crc_hqx(b"abcd", 0))
crc8 = crcToBf(CRC_8_CCITT)
crc8_aes = crcToBf(CRC_8_SAE_J1850)
cur8 = [0 for _ in range(8)]
c2 = [selectBit(0xC2, i) for i in range(8)]
self.assertEqual(naive_crc(c2, cur8, crc8_aes), 0xF)
c = [selectBit(ord("c"), i) for i in range(8)]
self.assertEqual(naive_crc(c, cur8, crc8), 0x2E)
cur8_half_1 = [selectBit(0x0f, i) for i in range(8)]
self.assertEqual(naive_crc(c2, cur8_half_1, crc8_aes), 0xB4)
self.assertEqual(naive_crc(c, cur8_half_1, crc8_aes), 0x8)
ab = [selectBit(stoi("ab"), i) for i in range(16)]
self.assertEqual(naive_crc(ab, cur8, crc8_aes), 0x7D)
self.assertEqual(naive_crc(ab, cur8_half_1, crc8_aes), 0xDE)
_12 = [selectBit(0x0102, i) for i in range(16)]
self.assertEqual(naive_crc(_12, cur8, crc8_aes), 0x85)
self.assertEqual(naive_crc(_12, cur8_half_1, crc8_aes), 0x26)
self.assertEqual(naive_crc(_12, cur8_half_1, crc8_aes, refin=True),
0x6F)
cur32 = [0 for _ in range(32)]
_crc32 = crcToBf(CRC_32)
self.assertEqual(naive_crc(c, cur32, _crc32), 0xA1E6E04E)
_s = ("0x00000000 0x04C11DB7 0x09823B6E 0x0D4326D9\n"
"0x130476DC 0x17C56B6B 0x1A864DB2 0x1E475005\n")
assert len(_s) % 4 == 0
s = stoi(_s)
s = [selectBit(s, i) for i in range(len(_s) * 8)]
self.assertEqual(naive_crc(s, cur32, _crc32), 0x59F59BE0)
cur32_1 = [1 for _ in range(32)]
self.assertEqual(naive_crc(s, cur32_1, _crc32), 0x141026C0)
self.assertEqual(naive_crc(s, cur32, _crc32, refout=True), 0x07D9AF9A)
self.assertEqual(naive_crc(s, cur32_1, _crc32, refout=True),
0x03640828)
self.assertEqual(naive_crc(s, cur32, _crc32, refin=True), 0xAE007AB1)
self.assertEqual(naive_crc(s, cur32_1, _crc32, refin=True), 0xE3E5C791)
self.assertEqual(naive_crc(s, cur32, _crc32, refin=True, refout=True),
0x8D5E0075)
self.assertEqual(
naive_crc(s, cur32_1, _crc32, refin=True, refout=True), 0x89E3A7C7)
self.assertEqual(
naive_crc(s, cur32_1, _crc32, refin=True, refout=True)
^ 0xffffffff, crc32(_s.encode()))
def test_parsePolyStr(self):
crc32_str = "x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1"
poly = parsePolyStr(crc32_str, 32)
expected = [selectBit(CRC_32.POLY, i) for i in range(CRC_32.WIDTH)]
self.assertEqual(poly, expected)
