def _copyParamsAndInterfaces(self):
for p in self._baseUnit._params:
myP = Param(p.get_value())
self._registerParameter(p._name, myP)
myP.set_value(p.get_value())
origToWrapInfMap = {}
for intf in self.baseUnit._interfaces:
# clone interface
myIntf = intf.__copy__()
# sub-interfaces are not instantiated yet
# myIntf._direction = intf._direction
myIntf._direction = INTF_DIRECTION.opposite(intf._direction)
self._registerInterface(intf._name, myIntf)
object.__setattr__(self, intf._name, myIntf)
origToWrapInfMap[intf] = myIntf
ei = self._ctx.interfaces
for i in self._interfaces:
self._loadInterface(i, True)
assert i._isExtern
i._signalsForInterface(self._ctx,
ei,
self._store_manager.name_scope,
reverse_dir=True)
return origToWrapInfMap
def _setDirectionsLikeIn(self, intfDir):
assert intfDir in [INTF_DIRECTION.MASTER,
INTF_DIRECTION.SLAVE,
INTF_DIRECTION.TRISTATE], intfDir
d = DIRECTION.asIntfDirection(self._masterDir)
if intfDir == INTF_DIRECTION.MASTER or d == INTF_DIRECTION.TRISTATE:
pass
else:
d = INTF_DIRECTION.opposite(d)
self._direction = d
for i in self._interfaces:
i._setDirectionsLikeIn(d)
def addPortToLNode(ln: LNode, intf: Interface, reverseDirection=False):
origin = originObjOfPort(intf)
d = intf._direction
if intf._masterDir == DIRECTION.IN:
d = INTF_DIRECTION.opposite(d)
d = PortTypeFromDir(d)
if reverseDirection:
d = PortType.opposite(d)
p = LNodeAddPortFromHdl(ln, origin, d, intf._name)
for _intf in intf._interfaces:
_addPort(ln, p, _intf, reverseDirection=reverseDirection)
return p
def _boundIntfSignalToEntity(self, interface, inftToPortDict):
portItem = single(self._entity.ports,
lambda x: x._interface == interface)
interface._boundedEntityPort = portItem
d = INTF_DIRECTION.asDirection(interface._direction)
if d == DIRECTION.INOUT:
portItem.direction = DIRECTION.INOUT
if portItem.direction != d:
raise IntfLvlConfErr(
("Unit %s: Port %s does not have direction "
" defined by interface %s, is %s should be %s") %
(self._name, portItem.name, repr(interface),
portItem.direction, d))
def addPort(n: LNode, intf: Interface):
"""
Add LayoutExternalPort for interface and LPort instances to this LNode
"""
d = intf._direction
if intf._masterDir == DIRECTION.IN:
d = INTF_DIRECTION.opposite(d)
d = PortTypeFromDir(d)
ext_p = LayoutExternalPort(n,
name=intf._name,
direction=d,
node2lnode=n._node2lnode,
originObj=originObjOfPort(intf))
n.children.append(ext_p)
addPortToLNode(ext_p, intf, reverseDirection=True)
return ext_p
def _copyParamsAndInterfaces(self):
for p in self._baseUnit._params:
myP = Param(evalParam(p))
self._registerParameter(p.name, myP)
object.__setattr__(self, myP.name, myP)
origToWrapInfMap = {}
for intf in self.baseUnit._interfaces:
# clone interface
myIntf = intf._clone()
# subinterfaces are not instanciated yet
# myIntf._direction = intf._direction
myIntf._direction = INTF_DIRECTION.opposite(intf._direction)
self._registerInterface(intf._name, myIntf)
object.__setattr__(self, intf._name, myIntf)
origToWrapInfMap[intf] = myIntf
for i in self._interfaces:
self._loadInterface(i, True)
return origToWrapInfMap
def _copyParamsAndInterfaces(self):
for p in self._baseUnit._params:
myP = Param(evalParam(p))
self._registerParameter(p.name, myP)
object.__setattr__(self, myP.name, myP)
origToWrapInfMap = {}
for intf in self.baseUnit._interfaces:
# clone interface
myIntf = intf._clone()
# subinterfaces are not instanciated yet
# myIntf._direction = intf._direction
myIntf._direction = INTF_DIRECTION.opposite(intf._direction)
self._registerInterface(intf._name, myIntf)
object.__setattr__(self, intf._name, myIntf)
origToWrapInfMap[intf] = myIntf
for i in self._interfaces:
self._loadInterface(i, True)
return origToWrapInfMap
def _signalsForInterface(self,
ctx: RtlNetlist,
res: Optional[Dict[RtlSignal, DIRECTION]],
name_scope: Optional[NameScope],
prefix='',
typeTransform=None,
reverse_dir=False):
"""
Generate RtlSignal _sig and HdlPortInstance _hdl_port
for each interface which has no subinterface
:note: if already has _sig return use it instead
:param ctx: instance of RtlNetlist where signals should be created
:param res: output dictionary where result should be stored
:param prefix: name prefix for created signals
:param name_scope: name scope used to check colisions on port names
if this a current top (every component is checked
when it is seen first time)
:param typeTransform: optional function (type) returns modified type
for signal
"""
if self._interfaces:
for intf in self._interfaces:
intf._signalsForInterface(ctx,
res,
name_scope,
prefix=prefix,
typeTransform=typeTransform,
reverse_dir=reverse_dir)
else:
assert self._sig is None, self
t = self._dtype
if typeTransform is not None:
t = typeTransform(t)
s = ctx.sig(prefix + self._getPhysicalName(), t)
s._interface = self
self._sig = s
if self._isExtern:
d = INTF_DIRECTION.asDirection(self._direction)
u = ctx.parent
if reverse_dir:
d = DIRECTION.opposite(d)
assert self._hdl_port is None, (
"Now creating a hdl interface for top"
" it but seems that it was already created")
if res is not None:
res[s] = d
if reverse_dir:
pi = portItemfromSignal(s, u, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
ctx.ent.ports.append(pi)
else:
pi = self._hdl_port
# port of some subcomponent which names were already checked
pi.connectOuterSig(s)
self._hdl_port = pi
def _reverseDirection(self):
"""Reverse direction of this interface in implementation stage"""
self._direction = INTF_DIRECTION.opposite(self._direction)
for intf in self._interfaces:
intf._reverseDirection()
