def synthesize(self, name, interfaces, targetPlatform): """ Build Entity and Architecture instance out of netlist representation """ ent = Entity(name) ent._name = name + "_inst" # instance name # create generics for _, v in self.params.items(): ent.generics.append(v) # interface set for faster lookup if isinstance(interfaces, set): intfSet = interfaces else: intfSet = set(interfaces) # create ports for s in interfaces: pi = portItemfromSignal(s, ent) pi.registerInternSig(s) ent.ports.append(pi) s.hidden = False removeUnconnectedSignals(self) markVisibilityOfSignals(self, name, self.signals, intfSet) for proc in targetPlatform.beforeHdlArchGeneration: proc(self) arch = Architecture(ent) for p in statements_to_HWProcesses(self.statements): arch.processes.append(p) # add signals, variables etc. in architecture for s in self.signals: if s not in intfSet and not s.hidden: arch.variables.append(s) # instantiate subUnits in architecture for u in self.subUnits: arch.componentInstances.append(u) # add components in architecture for su in distinctBy(self.subUnits, lambda x: x.name): arch.components.append(su) self.synthesised = True return [ent, arch]
def makeTestbenchTemplate(unit: Unit, name: str=None): """ :param unit: synthesized unit :return: (entity, arch, context) of testbench """ if name is None: name = unit._name + "_tb" entity = Entity(name) arch = Architecture(entity) arch.components.append(unit._entity) arch.componentInstances.append(unit._entity) nl = RtlNetlist() ctx = {} for p in unit._entity.ports: t = p._dtype if isinstance(t, Bits) and not t == BIT: t = Bits(t.bit_length(), signed=t.signed, forceVector=t.forceVector) s = RtlSignal(nl, p.name, t, t.fromPy(0)) ctx[p._interface] = s p.connectSig(s) arch.variables.extend(ctx.values()) return entity, arch, ctx
def Entity(cls, ent: Entity, ctx: SerializerCtx): """ Entity is just forward declaration of Architecture, it is not used in most HDL languages as there is no recursion in hierarchy """ ent.name = ctx.scope.checkedName(ent.name, ent, isGlobal=True) return ""
def Entity(cls, ent: Entity, ctx: HwtSerializerCtx): """ Entity is just forward declaration of Architecture, it is not used in most HDL languages as there is no recursion in hierarchy """ cls.Entity_prepare(ent, ctx, serialize=False) ent.name = ctx.scope.checkedName(ent.name, ent, isGlobal=True) ports = list( map(lambda p: (p.name, cls.HdlType(p._dtype, ctx)), ent.ports)) return unitHeadTmpl.render( name=ent.name, ports=ports, )
def ComponentInstance(cls, entity: Entity, ctx): with CurrentUnitSwap(ctx, entity.origin): portMaps = [] for pi in entity.ports: pm = PortMap.fromPortItem(pi) portMaps.append(pm) genericMaps = [] for g in entity.generics: gm = MapExpr(g, g._val) genericMaps.append(gm) if len(portMaps) == 0: raise SerializerException("Incomplete component instance") entity._name = ctx.scope.checkedName(entity._name, entity) return cls.componentInstanceTmpl.render( indent=getIndent(ctx.indent), instanceName=entity._name, entity=entity, portMaps=[cls.PortConnection(x, ctx) for x in portMaps], genericMaps=[cls.MapExpr(x, ctx) for x in genericMaps])