def postProcess(self, component: Component, packager: IpPackager, thisIf: Axi3Lite):
self.endianness = "little"
thisIntfName = packager.getInterfaceLogicalName(thisIf)
self.addWidthParam(thisIntfName, "ADDR_WIDTH", thisIf.ADDR_WIDTH, packager)
self.addWidthParam(thisIntfName, "DATA_WIDTH", thisIf.DATA_WIDTH, packager)
self.addSimpleParam(thisIntfName, "PROTOCOL", "AXI4LITE")
self.addSimpleParam(thisIntfName, "READ_WRITE_MODE", "READ_WRITE")
def postProcess(self, component: Component, packager: IpPackager,
thisIf: Axi3Lite):
self.endianness = "little"
thisIntfName = packager.getInterfaceLogicalName(thisIf)
self.addWidthParam(thisIntfName, "ADDR_WIDTH", thisIf.ADDR_WIDTH,
packager)
self.addWidthParam(thisIntfName, "DATA_WIDTH", thisIf.DATA_WIDTH,
packager)
self.addSimpleParam(thisIntfName, "PROTOCOL", "AXI4LITE")
self.addSimpleParam(thisIntfName, "READ_WRITE_MODE", "READ_WRITE")
def postProcess(self, component: Component, packager: IpPackager,
thisIf: Axi3):
self.endianness = "little"
thisIntfName = packager.getInterfaceLogicalName(thisIf)
def param(name, val):
return self.addSimpleParam(thisIntfName, name, str(val))
# [TODO] width as expression instead of int
param("ADDR_WIDTH", thisIf.aw.addr._dtype.bit_length())
param("MAX_BURST_LENGTH", int(2**thisIf.aw.len._dtype.bit_length()))
param("NUM_READ_OUTSTANDING", 5)
param("NUM_WRITE_OUTSTANDING", 5)
param("PROTOCOL", self.xilinx_protocol_name)
param("READ_WRITE_MODE", "READ_WRITE")
param("SUPPORTS_NARROW_BURST", 0)
A_U_W = int(thisIf.ADDR_USER_WIDTH)
if A_U_W:
param("AWUSER_WIDTH", A_U_W)
param("ARUSER_WIDTH", A_U_W)
def postProcess(self, component: Component, packager: IpPackager,
thisIf: Rst_n):
self.addSimpleParam(packager.getInterfaceLogicalName(thisIf),
"POLARITY", "ACTIVE_LOW")