def test_SimpleUnit2(self):
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
def ex(i):
return self.assertTrue(i._isExtern)
ex(u.a)
ex(u.a.data)
ex(u.a.last)
ex(u.a.ready)
ex(u.a.strb)
ex(u.a.valid)
ex(u.b)
ex(u.b.data)
ex(u.b.last)
ex(u.b.ready)
ex(u.b.strb)
ex(u.b.valid)
u = synthesised(u)
for pn in ['a_data', 'a_last', 'a_strb', 'a_valid', 'b_ready']:
self.assertDirIn(u, pn)
for pn in ['a_ready', 'b_data', 'b_last', 'b_strb', 'b_valid']:
self.assertDirOut(u, pn)
def test_SimpleUnit2(self):
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
def ex(i): return self.assertTrue(i._isExtern)
ex(u.a)
ex(u.a.data)
ex(u.a.last)
ex(u.a.ready)
ex(u.a.strb)
ex(u.a.valid)
ex(u.b)
ex(u.b.data)
ex(u.b.last)
ex(u.b.ready)
ex(u.b.strb)
ex(u.b.valid)
u = synthesised(u)
for pn in ['a_data', 'a_last', 'a_strb', 'a_valid', 'b_ready']:
self.assertDirIn(u, pn)
for pn in ['a_ready', 'b_data', 'b_last', 'b_strb', 'b_valid']:
self.assertDirOut(u, pn)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.subunit0 = SimpleUnitAxiStream()
self.a0 = AxiStream()
self.b0 = AxiStream()._m()
def test_SimpleUnit2_iLvl(self):
"""
Check interface directions pre and after synthesis
"""
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
m = self.assertIsM
s = self.assertIsS
# u.a._resolveDirections()
# u.b._resolveDirections()
#
#
# # inside
# m(u.a)
# m(u.a.data)
# m(u.a.last)
# s(u.a.ready)
# m(u.a.valid)
# m(u.a.strb)
#
# # inside
# m(u.b)
# m(u.b.data)
# m(u.b.last)
# s(u.b.ready)
# m(u.b.valid)
# m(u.b.strb)
u = synthesised(u)
# outside
s(u.a)
s(u.a.data)
s(u.a.last)
m(u.a.ready)
s(u.a.valid)
s(u.a.strb)
m(u.b)
m(u.b.data)
m(u.b.last)
s(u.b.ready)
m(u.b.valid)
m(u.b.strb)
def test_SimpleUnit2_iLvl(self):
"""
Check interface directions pre and after synthesis
"""
from hwtLib.examples.simpleAxiStream import SimpleUnitAxiStream
u = SimpleUnitAxiStream()
u._loadDeclarations()
m = self.assertIsM
s = self.assertIsS
# u.a._resolveDirections()
# u.b._resolveDirections()
#
#
# # inside
# m(u.a)
# m(u.a.data)
# m(u.a.last)
# s(u.a.ready)
# m(u.a.valid)
# m(u.a.strb)
#
# # inside
# m(u.b)
# m(u.b.data)
# m(u.b.last)
# s(u.b.ready)
# m(u.b.valid)
# m(u.b.strb)
u = synthesised(u)
# outside
s(u.a)
s(u.a.data)
s(u.a.last)
m(u.a.ready)
s(u.a.valid)
s(u.a.strb)
m(u.b)
m(u.b.data)
m(u.b.last)
s(u.b.ready)
m(u.b.valid)
m(u.b.strb)
def test_SimpleUnitAxiStream(self):
u = SimpleUnitAxiStream()
g = convert(u)
root = g[0]
# interface is merged to only single connection
self.assertEqual(len(root.children), 2)
self.assertEqual(len(root.children[0].east), 1)
self.assertEqual(len(root.children[1].west), 1)
def _declr(self):
SimpleUnitAxiStream._declr(self)
addClkRstn(self)
def _declr(self):
SimpleUnitAxiStream._declr(self)
addClkRstn(self)