class RamWithHs(RamAsHs):
def _declr(self):
addClkRstn(self)
with self._paramsShared():
if self.HAS_R:
self.r = RamHsR()
if self.HAS_W:
self.w = AddrDataHs()
self.conv = RamAsHs()
r = self.ram = RamSingleClock()
if not self.HAS_W:
assert self.INIT_DATA is not None
assert self.HAS_R
r.PORT_CNT = (READ,)
elif not self.HAS_R:
assert self.HAS_W
r.PORT_CNT = (WRITE,)
def _impl(self):
propagateClkRstn(self)
if self.HAS_R:
self.conv.r(self.r)
if self.HAS_W:
self.conv.w(self.w)
self.ram.port[0](self.conv.ram)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.r = RamHsR()
self.w = AddrDataHs()
self.conv = RamAsHs()
self.ram = RamSingleClock()
class RamWithHs(RamAsHs):
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.r = RamHsR()
self.w = AddrDataHs()
self.conv = RamAsHs()
self.ram = RamSingleClock()
def _impl(self):
propagateClkRstn(self)
self.conv.r(self.r)
self.conv.w(self.w)
self.ram.a(self.conv.ram)
class RamWithHs(RamAsHs):
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.r = RamHsR()
self.w = AddrDataHs()
self.conv = RamAsHs()
self.ram = RamSingleClock()
def _impl(self):
propagateClkRstn(self)
self.conv.r(self.r)
self.conv.w(self.w)
self.ram.a(self.conv.ram)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.r = RamHsR()
self.w = AddrDataHs()
self.conv = RamAsHs()
self.ram = RamSingleClock()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
if self.HAS_R:
self.r = RamHsR()
if self.HAS_W:
self.w = AddrDataHs()
self.conv = RamAsHs()
r = self.ram = RamSingleClock()
if not self.HAS_W:
assert self.INIT_DATA is not None
assert self.HAS_R
r.PORT_CNT = (READ,)
elif not self.HAS_R:
assert self.HAS_W
r.PORT_CNT = (WRITE,)
def _declr(self):
HashTableCoreWithRam._declr_common(self)
t = self.table = RamSingleClock()
t.PORT_CNT = 1
t.ADDR_WIDTH = log2ceil(self.ITEMS_CNT)
t.DATA_WIDTH = self.KEY_WIDTH + self.DATA_WIDTH + 1 # +1 for item_vld
tc = self.tableConnector = RamAsHs()
tc.ADDR_WIDTH = t.ADDR_WIDTH
tc.DATA_WIDTH = t.DATA_WIDTH
def _declr(self):
self.PAGE_OFFSET_WIDTH = log2ceil(self.PAGE_SIZE).val
self.LVL1_PAGE_TABLE_INDX_WIDTH = log2ceil(
self.LVL1_PAGE_TABLE_ITEMS).val
self.LVL2_PAGE_TABLE_INDX_WIDTH = int(self.ADDR_WIDTH -
self.LVL1_PAGE_TABLE_INDX_WIDTH -
self.PAGE_OFFSET_WIDTH)
self.LVL2_PAGE_TABLE_ITEMS = 2**int(self.LVL2_PAGE_TABLE_INDX_WIDTH)
assert self.LVL1_PAGE_TABLE_INDX_WIDTH > 0, self.LVL1_PAGE_TABLE_INDX_WIDTH
assert self.LVL2_PAGE_TABLE_INDX_WIDTH > 0, self.LVL2_PAGE_TABLE_INDX_WIDTH
assert self.LVL2_PAGE_TABLE_ITEMS > 1, self.LVL2_PAGE_TABLE_ITEMS
# public interfaces
addClkRstn(self)
with self._paramsShared():
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1)
i = self.virtIn = Handshaked()
i._replaceParam(i.DATA_WIDTH, self.VIRT_ADDR_WIDTH)
i = self.physOut = Handshaked()._m()
i._replaceParam(i.DATA_WIDTH, self.ADDR_WIDTH)
self.segfault = Signal()._m()
self.lvl1Table = BramPort_withoutClk()
# internal components
self.lvl1Storage = RamSingleClock()
self.lvl1Storage.PORT_CNT.set(1)
self.lvl1Converter = RamAsHs()
for u in [self.lvl1Table, self.lvl1Converter, self.lvl1Storage]:
u.DATA_WIDTH.set(self.ADDR_WIDTH)
u.ADDR_WIDTH.set(self.LVL1_PAGE_TABLE_INDX_WIDTH)
with self._paramsShared():
self.lvl2get = ArrayItemGetter()
self.lvl2get.ITEM_WIDTH.set(self.ADDR_WIDTH)
self.lvl2get.ITEMS.set(self.LVL2_PAGE_TABLE_ITEMS)
self.lvl2indxFifo = HandshakedFifo(Handshaked)
self.lvl2indxFifo.DEPTH.set(self.MAX_OVERLAP // 2)
self.lvl2indxFifo.DATA_WIDTH.set(self.LVL2_PAGE_TABLE_INDX_WIDTH)
self.pageOffsetFifo = HandshakedFifo(Handshaked)
self.pageOffsetFifo.DEPTH.set(self.MAX_OVERLAP)
self.pageOffsetFifo.DATA_WIDTH.set(self.PAGE_OFFSET_WIDTH)
def instantiate_data_array_to_hs(
self,
data_arr_r_port: BramPort_withoutClk,
data_arr_w_port: BramPort_withoutClk,
):
"""
Convert bram ports of data array to a handshaked interfaces
"""
data_arr_r_to_hs = RamAsHs()
data_arr_w_to_hs = RamAsHs()
data_arr_r_to_hs._updateParamsFrom(data_arr_r_port)
data_arr_w_to_hs._updateParamsFrom(data_arr_w_port)
self.data_arr_r_to_hs = data_arr_r_to_hs
self.data_arr_w_to_hs = data_arr_w_to_hs
data_arr_r_port(data_arr_r_to_hs.ram)
data_arr_w_port(data_arr_w_to_hs.ram)
return data_arr_r_to_hs.r, data_arr_w_to_hs.w
def _declr(self):
addClkRstn(self)
assert int(self.KEY_WIDTH) > 0
assert int(self.DATA_WIDTH) >= 0
assert int(self.ITEMS_CNT) > 1
self.HASH_WITH = log2ceil(self.ITEMS_CNT).val
assert self.HASH_WITH < int(self.KEY_WIDTH), (
"It makes no sense to use hash table when you can use key directly as index",
self.HASH_WITH, self.KEY_WIDTH)
with self._paramsShared():
self.insert = InsertIntf()
self.insert.HASH_WIDTH.set(self.HASH_WITH)
self.lookup = LookupKeyIntf()
self.lookupRes = LookupResultIntf()._m()
self.lookupRes.HASH_WIDTH.set(self.HASH_WITH)
t = self.table = RamSingleClock()
t.PORT_CNT.set(1)
t.ADDR_WIDTH.set(log2ceil(self.ITEMS_CNT))
t.DATA_WIDTH.set(self.KEY_WIDTH + self.DATA_WIDTH +
1) # +1 for vldFlag
tc = self.tableConnector = RamAsHs()
tc.ADDR_WIDTH.set(t.ADDR_WIDTH.get())
tc.DATA_WIDTH.set(t.DATA_WIDTH.get())
hashWidth = max(int(self.KEY_WIDTH), int(self.HASH_WITH))
h = self.hash = CrcComb()
h.DATA_WIDTH.set(hashWidth)
h.setConfig(self.POLYNOME)
h.POLY_WIDTH.set(hashWidth)