def _declr(self):
AxiWriteAggregatorWriteDispatcher.precompute_constants(self)
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.m = Axi4()._m()
if self.BUS_WORDS_IN_CACHE_LINE > 1:
fb = AxiSFifoCopy(Axi4_r)
fb.DEPTH = 2 * self.BUS_WORDS_IN_CACHE_LINE
else:
fb = AxiSRegCopy(Axi4_r)
self.frame_buff = fb
ac = self.addr_cam = CamMultiPort()
ac.MATCH_PORT_CNT = 1
ac.ITEMS = 2**self.ID_WIDTH
ac.USE_VLD_BIT = False
ac.KEY_WIDTH = self.CACHE_LINE_ADDR_WIDTH
for i in [self.s, self.m]:
i.HAS_W = False
def _impl(self):
CamMultiPort._impl(self)
self.read.data(self._mem[self.read.addr])
def _declr(self):
assert not self.USE_VLD_BIT
CamMultiPort._declr(self)
r = self.read = AddrDataIntf()
r.ADDR_WIDTH = log2ceil(self.ITEMS - 1)
r.DATA_WIDTH = self.KEY_WIDTH
def _config(self):
CamMultiPort._config(self)
self.USE_VLD_BIT = False