def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH = 16
en0 = AxiS_en()
en0.USE_STRB = True
en0.USE_KEEP = True
en0.ID_WIDTH = 8
en0.DEST_WIDTH = 4
en0.USER_WIDTH = 12
u0 = SimpleUnitWithParam()
u0.DATA_WIDTH = 2
u1 = SimpleUnitWithParam()
u1.DATA_WIDTH = 3
u_with_hdl_params = MultiConfigUnitWrapper([u0, u1])
testUnits = [
AxiS_en(),
en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(),
f,
Axi4streamToMem(),
IpCoreIntfTest(),
u_with_hdl_params,
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def setUp(self):
super(FifoTC, self).setUp()
u = self.u = Fifo()
u.DATA_WIDTH.set(8)
u.DEPTH.set(self.ITEMS)
u.EXPORT_SIZE.set(True)
self.prepareUnit(u)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dataIn = self.intfCls()
self.dataOut = self.intfCls()._m()
f = self.fifo = Fifo()
DW = self.dataIn._bit_length() - 2 # 2 for control (valid, ready)
f.DATA_WIDTH.set(DW)
f.DEPTH.set(self.DEPTH - 1) # because there is an extra register
f.EXPORT_SIZE.set(self.EXPORT_SIZE)
if self.EXPORT_SIZE:
self.size = VectSignal(log2ceil(self.DEPTH + 1 + 1),
signed=False)._m()
def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH.set(16)
en0 = AxiS_en()
en0.USE_STRB.set(True)
en0.USE_KEEP.set(True)
en0.ID_WIDTH.set(8)
en0.DEST_WIDTH.set(4)
en0.USER_WIDTH.set(12)
testUnits = [
AxiS_en(), en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(), f,
Axi4streamToMem(),
IpCoreIntfTest()
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def _impl(self):
propagateClkRstn(self)
ITEMS = self.ITEMS
# 1 if item contains valid item which can be read
item_valid = self._reg("item_valid", Bits(ITEMS), def_val=0)
# 1 if item can not be update any more (:note: valid=1)
item_write_lock = self._reg("item_write_lock", Bits(ITEMS), def_val=0)
write_req, write_wait = self._sig("write_req"), self._sig("write_wait")
read_req, read_wait = self._sig("read_req"), self._sig("read_wait")
(write_en, write_ptr), (read_en, read_ptr) = Fifo.fifo_pointers(
self, ITEMS, (write_req, write_wait), [
(read_req, read_wait),
])
write_confirm = self.write_confirm
write_req(write_confirm.vld & ~write_wait & ~item_valid[write_ptr])
write_confirm.rd(~write_wait & ~item_valid[write_ptr])
read_execute = self.read_execute
read_req(read_execute.rd & ~read_wait)
read_execute.vld(~read_wait)
read_execute.index(read_ptr)
# out of order read confirmation
pc = self.read_confirm
pc.rd(1)
_vld_next = []
_item_write_lock_next = []
for i in range(ITEMS):
vld_next = self._sig(f"valid_{i:d}_next")
item_write_lock_next = self._sig(f"item_write_lock_{i:d}_next")
If(
pc.vld & pc.data._eq(i),
# this is an item which we are discarding
vld_next(0),
item_write_lock_next(0)
).Elif(
write_en & write_ptr._eq(i),
# this is an item which we will write
vld_next(1),
item_write_lock_next(0),
).Elif(
read_ptr._eq(i) | (read_ptr._eq((i - 1) % ITEMS) & read_req),
# we will start reading this item or we are already reading this item
vld_next(item_valid[i]),
item_write_lock_next(item_valid[i]),
).Else(
vld_next(item_valid[i]),
item_write_lock_next(item_write_lock[i]),
)
_vld_next.append(vld_next)
_item_write_lock_next.append(item_write_lock_next)
item_valid(Concat(*reversed(_vld_next)))
item_write_lock(Concat(*reversed(_item_write_lock_next)))
return item_valid, item_write_lock, (write_en, write_ptr), (read_en,
read_ptr)
def setUpClass(cls):
u = cls.u = Fifo()
u.DATA_WIDTH = 8
u.DEPTH = cls.ITEMS
u.EXPORT_SIZE = True
cls.compileSim(cls.u)
def _config(self):
Fifo._config(self)
self.IN_FREQ = Param(int(100e6))
self.OUT_FREQ = Param(int(100e6))