def test_controller(self):
i = inc([1, 2, 3])
self.assertEqual(i.controller(), [1, 2, 4])
i = inc([1, 2, 0])
self.assertEqual(i.controller(), [1, 2, 1])
i = inc([1, 9, 9])
self.assertEqual(i.controller(), [2, 0, 0])
def test_controller(self):
i = inc([1, 2, 3])
self.assertEqual(i.controller(), [1, 2, 4])
i = inc([1, 2, 0])
self.assertEqual(i.controller(), [1, 2, 1])
i = inc([1, 9, 9])
self.assertEqual(i.controller(), [2, 0, 0])
def testbench():
m = 3
count = Signal(modbv(0)[m:])
enable = Signal(bool(0))
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
inc_1 = inc(count, enable, clock, reset)
HALF_PERIOD = delay(10)
@always(HALF_PERIOD)
def clockGen():
clock.next = not clock
@instance
def stimulus():
reset.next = ACTIVE_LOW
yield clock.negedge
reset.next = INACTIVE_HIGH
for i in range(16):
enable.next = min(1, randrange(3))
yield clock.negedge
raise StopSimulation()
@instance
def monitor():
print("enable count")
yield reset.posedge
while 1:
yield clock.posedge
yield delay(1)
print(" %s %s" % (int(enable), count))
return clockGen, stimulus, inc_1, monitor
def gray_inc(graycnt, enable, clock, reset, width):
bincnt = Signal(modbv(0)[width:])
inc_0 = inc(bincnt, enable, clock, reset)
bin2gray_0 = bin2gray(B=bincnt, G=graycnt)
return inc_0, bin2gray_0
def bench(self):
n = 253
count, enable, clock, reset = [Signal(intbv(0)) for i in range(4)]
INC_1 = inc(count, enable, clock, reset, n=n)
CLK_1 = self.clockGen(clock)
ST_1 = self.stimulus(enable, clock, reset)
CH_1 = self.check(count, enable, clock, reset, n=n)
sim = Simulation(INC_1, CLK_1, ST_1, CH_1)
return sim
def convert_inc(hdl):
"""Convert inc block to Verilog or VHDL."""
m = 8
count = Signal(modbv(0)[m:])
enable = Signal(bool(0))
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
inc_1 = inc(count, enable, clock, reset)
inc_1.convert(hdl=hdl)
def convert_inc(hdl):
"""Convert inc block to Verilog or VHDL."""
m = 8
count = Signal(modbv(0)[m:])
enable = Signal(bool(0))
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
inc_1 = inc(count, enable, clock, reset)
inc_1.convert(hdl=hdl)
def bench(self):
n = 253
count, enable, clock, reset = [Signal(intbv(0)) for i in range(4)]
INC_1 = inc(count, enable, clock, reset, n=n)
CLK_1 = self.clockGen(clock)
ST_1 = self.stimulus(enable, clock, reset)
CH_1 = self.check(count, enable, clock, reset, n=n)
sim = Simulation(INC_1, CLK_1, ST_1, CH_1)
return sim
def test_inc():
assert inc(3) == 4
def test_inc():
assert (inc(3) == 4)
def test_my_function(self):
self.assertEqual(inc(0), 1)
self.assertEqual(inc(100), 101)
self.assertEqual(inc(1), 2)
self.assertEqual(inc(-1), 0)
from myhdl import toVerilog, toVHDL, Signal, ResetSignal, modbv from inc import inc ACTIVE_LOW, INACTIVE_HIGH = 0, 1 # conversion m = 8 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) inc_inst = inc(count, enable, clock, reset) inc_inst = toVerilog(inc, count, enable, clock, reset) inc_inst = toVHDL(inc, count, enable, clock, reset)
import time import inc print inc.inc(3,3) a = range(100000) import time t1 = time.time() b = inc.inc_seq(a,3) t2 = time.time() normal = t2-t1 print 'normal:', normal t1 = time.time() b = inc.fast_inc_seq(a,3) t2 = time.time() fast = t2-t1 print 'fast:', fast print 'speedup:', normal/fast
#import inc from inc import inc, dec print inc(5) print dec(9)
from myhdl import toVerilog, toVHDL, Signal, ResetSignal, modbv from inc import inc ACTIVE_LOW, INACTIVE_HIGH = 0, 1 # conversion m = 8 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) inc_inst = inc(count, enable, clock, reset) inc_inst = toVerilog(inc, count, enable, clock, reset) inc_inst = toVHDL(inc, count, enable, clock, reset)
import inc print inc.inc(3,3) a = range(100000) import time t1 = time.time() b = inc.inc_seq(a,3) t2 = time.time() normal = t2-t1 print 'normal:', normal t1 = time.time() b = inc.fast_inc_seq(a,3) t2 = time.time() fast = t2-t1 print 'fast:', fast print 'speedup:', normal/fast
